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Re: [RFC v2 08/15] target/riscv: rvb: single-bit instructions
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v2 08/15] target/riscv: rvb: single-bit instructions |
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Date: |
Wed, 16 Dec 2020 10:34:14 -0600 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool gen_shifti(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_movi_tl(source2, a->shamt);
> +
> + tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
Don't make the tcg optimizer do what it's easy to do in C, e.g.
tcg_gen_movi_tl(source2, a->shamt & (TARGET_LONG_BITS - 1));
Except in this case, I believe that shamt *cannot* be out of range, because
that would be an illegal instruction. E.g. in trans_srli, we check for that
first.
In the previous review I had recommended that you convert the existing
immediate shift instructions to this new interface, which should have shown
this problem.
> +static bool gen_shiftiw(DisasContext *ctx, arg_shift *a,
> + void(*func)(TCGv, TCGv, TCGv))
> +{
> + TCGv source1 = tcg_temp_new();
> + TCGv source2 = tcg_temp_new();
> +
> + gen_get_gpr(source1, a->rs1);
> + tcg_gen_movi_tl(source2, a->shamt);
> +
> + tcg_gen_andi_tl(source2, source2, 31);
This mask is unnecesary because the decode already uses @sh5.
r~
- Re: [RFC v2 03/15] target/riscv: rvb: count bits set, (continued)
- [RFC v2 04/15] target/riscv: rvb: logic-with-negate, frank . chang, 2020/12/15
- [RFC v2 05/15] target/riscv: rvb: pack two words into one register, frank . chang, 2020/12/15
- [RFC v2 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/12/15
- [RFC v2 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/12/15
- [RFC v2 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/12/15
- Re: [RFC v2 08/15] target/riscv: rvb: single-bit instructions,
Richard Henderson <=
- [RFC v2 09/15] target/riscv: rvb: shift ones, frank . chang, 2020/12/15
- [RFC v2 10/15] target/riscv: rvb: rotate (left/right), frank . chang, 2020/12/15
- [RFC v2 12/15] target/riscv: rvb: generalized or-combine, frank . chang, 2020/12/15
- [RFC v2 13/15] target/riscv: rvb: address calculation, frank . chang, 2020/12/15
- [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend, frank . chang, 2020/12/15