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Re: [RFC v2 09/15] target/riscv: rvb: shift ones
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From: |
Richard Henderson |
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Subject: |
Re: [RFC v2 09/15] target/riscv: rvb: shift ones |
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Date: |
Wed, 16 Dec 2020 10:35:37 -0600 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 12/15/20 8:01 PM, frank.chang@sifive.com wrote:
> +static bool trans_sloi(DisasContext *ctx, arg_sloi *a)
> +{
> + REQUIRE_EXT(ctx, RVB);
> +
> + if (a->shamt >= TARGET_LONG_BITS) {
> + return false;
> + }
As I mentioned vs the previous patch, these checks should be in gen_shifti.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
- Re: [RFC v2 04/15] target/riscv: rvb: logic-with-negate, (continued)
- [RFC v2 05/15] target/riscv: rvb: pack two words into one register, frank . chang, 2020/12/15
- [RFC v2 06/15] target/riscv: rvb: min/max instructions, frank . chang, 2020/12/15
- [RFC v2 07/15] target/riscv: rvb: sign-extend instructions, frank . chang, 2020/12/15
- [RFC v2 08/15] target/riscv: rvb: single-bit instructions, frank . chang, 2020/12/15
- [RFC v2 09/15] target/riscv: rvb: shift ones, frank . chang, 2020/12/15
- Re: [RFC v2 09/15] target/riscv: rvb: shift ones,
Richard Henderson <=
- [RFC v2 10/15] target/riscv: rvb: rotate (left/right), frank . chang, 2020/12/15
- [RFC v2 12/15] target/riscv: rvb: generalized or-combine, frank . chang, 2020/12/15
- [RFC v2 13/15] target/riscv: rvb: address calculation, frank . chang, 2020/12/15
- [RFC v2 14/15] target/riscv: rvb: add/sub with postfix zero-extend, frank . chang, 2020/12/15
- [RFC v2 11/15] target/riscv: rvb: generalized reverse, frank . chang, 2020/12/15