[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 11/17] x86/cpu: Add AVX512_FP16 cpu feature
From: |
Eduardo Habkost |
Subject: |
[PULL 11/17] x86/cpu: Add AVX512_FP16 cpu feature |
Date: |
Thu, 17 Dec 2020 13:46:14 -0500 |
From: Cathy Zhang <cathy.zhang@intel.com>
AVX512 Half-precision floating point (FP16) has better performance
compared to FP32 if the presicion or magnitude requirements are met.
It's defined as CPUID.(EAX=7,ECX=0):EDX[bit 23].
Refer to
https://software.intel.com/content/www/us/en/develop/download/\
intel-architecture-instruction-set-extensions-programming-reference.html
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Message-Id: <20201216224002.32677-1-cathy.zhang@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
target/i386/cpu.h | 2 ++
target/i386/cpu.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index ee03263800..9b2ced97ea 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -784,6 +784,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_SERIALIZE (1U << 14)
/* TSX Suspend Load Address Tracking instruction */
#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
+/* AVX512_FP16 instruction */
+#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
/* Speculation Control */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
/* Single Thread Indirect Branch Predictors */
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 45b0588af3..608e9cacf9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -979,7 +979,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"avx512-vp2intersect", NULL, "md-clear", NULL,
NULL, NULL, "serialize", NULL,
"tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
- NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, "avx512-fp16",
NULL, NULL, "spec-ctrl", "stibp",
NULL, "arch-capabilities", "core-capability", "ssbd",
},
--
2.28.0
- [PULL 04/17] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs, (continued)
- [PULL 04/17] i386: hvf: remove stale MAINTAINERS entry for old hvf stubs, Eduardo Habkost, 2020/12/17
- [PULL 05/17] i386: move TCG accel files into tcg/, Eduardo Habkost, 2020/12/17
- [PULL 06/17] i386: move cpu dump out of helper.c into cpu-dump.c, Eduardo Habkost, 2020/12/17
- [PULL 07/17] i386: move hyperv_vendor_id initialization to x86_cpu_realizefn(), Eduardo Habkost, 2020/12/17
- [PULL 09/17] i386: move hyperv_version_id initialization to x86_cpu_realizefn(), Eduardo Habkost, 2020/12/17
- [PULL 08/17] i386: move hyperv_interface_id initialization to x86_cpu_realizefn(), Eduardo Habkost, 2020/12/17
- [PULL 13/17] i386: tcg: remove inline from cpu_load_eflags, Eduardo Habkost, 2020/12/17
- [PULL 10/17] i386: move hyperv_limits initialization to x86_cpu_realizefn(), Eduardo Habkost, 2020/12/17
- [PULL 12/17] i386: move TCG cpu class initialization to tcg/, Eduardo Habkost, 2020/12/17
- [PULL 15/17] tcg: make CPUClass.cpu_exec_* optional, Eduardo Habkost, 2020/12/17
- [PULL 11/17] x86/cpu: Add AVX512_FP16 cpu feature,
Eduardo Habkost <=
- [PULL 14/17] tcg: cpu_exec_{enter,exit} helpers, Eduardo Habkost, 2020/12/17
- [PULL 17/17] cpu: Remove unnecessary noop methods, Eduardo Habkost, 2020/12/17
- [PULL 16/17] tcg: Make CPUClass.debug_excp_handler optional, Eduardo Habkost, 2020/12/17
- Re: [PULL 00/17] x86 queue, 2020-12-17, Peter Maydell, 2020/12/17