Re: [PATCH v2 9/9] target/arm: use official org.gnu.gdb.aarch64.sve layout for registers

[Alex Bennée]

Alex Bennée <alex.bennee@linaro.org> writes:

> While GDB can work with any XML description given to it there is
> special handling for SVE registers on the GDB side which makes the
> users life a little better. The changes aren't that major and all the
> registers save the $vg reported the same. All that changes is:
>
>   - report org.gnu.gdb.aarch64.sve
>   - use gdb nomenclature for names and types
>   - minor re-ordering of the types to match reference
>   - re-enable ieee_half (as we know gdb supports it now)
>   - $vg is now a 64 bit int
>   - check $vN and $zN aliasing in test
>
> [NOTE: there seems a limitation on the indexing of the pseudo $vN
> registers which I'm not sure if it's intentional]

It is (v registers are the aliased vector registers, not an alternative
to the z register).
>  
> +        # check the v pseudo regs - I'm not sure if them capping out
> +        # at [15] is intentional though.

I'm going to change this comment to:

  Check the aliased V registers are set and GDB has correctly
  created them for us having recognised and handled SVE.

> +        try:
> +            for i in range(0, 16):
> +                val_z = gdb.parse_and_eval("$z0.b.u[%d]" % i)
> +                val_v = gdb.parse_and_eval("$v0.b.u[%d]" % i)
> +                report(int(val_z) == int(val_v),
> +                       "v0.b.u[%d] == z0.b.u[%d]" % (i, i))
> +        except gdb.error:
> +            report(False, "checking vregs (out of range)")
> +
>  
>  def run_test():
>      "Run through the tests one by one"


-- 
Alex Bennée