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[PATCH v3 06/30] target/arm: Move mode specific TB flags to tb->cs_base
From: |
Richard Henderson |
Subject: |
[PATCH v3 06/30] target/arm: Move mode specific TB flags to tb->cs_base |
Date: |
Mon, 11 Jan 2021 09:00:49 -1000 |
Now that we have all of the proper macros defined, expanding
the CPUARMTBFlags structure and populating the two TB fields
is relatively simple.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 49 ++++++++++++++++++++++++------------------
target/arm/translate.h | 2 +-
target/arm/helper.c | 2 +-
3 files changed, 30 insertions(+), 23 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c7700c9c85..af70462cfa 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -221,6 +221,7 @@ typedef struct ARMPACKey {
/* See the commentary above the TBFLAG field definitions. */
typedef struct CPUARMTBFlags {
uint32_t flags;
+ target_ulong flags2;
} CPUARMTBFlags;
typedef struct CPUARMState {
@@ -3251,20 +3252,26 @@ typedef ARMCPU ArchCPU;
#include "exec/cpu-all.h"
/*
- * Bit usage in the TB flags field: bit 31 indicates whether we are
- * in 32 or 64 bit mode. The meaning of the other bits depends on that.
- * We put flags which are shared between 32 and 64 bit mode at the top
- * of the word, and flags which apply to only one mode at the bottom.
+ * We have more than 32-bits worth of state per TB, so we split the data
+ * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
+ * We collect these two parts in CPUARMTBFlags where they are named
+ * flags and flags2 respectively.
*
- * 31 20 18 14 9 0
- * +--------------+-----+-----+----------+--------------+
- * | | | TBFLAG_A32 | |
- * | | +-----+----------+ TBFLAG_AM32 |
- * | TBFLAG_ANY | |TBFLAG_M32| |
- * | +-----------+----------+--------------|
- * | | TBFLAG_A64 |
- * +--------------+-------------------------------------+
- * 31 20 0
+ * The flags that are shared between all execution modes, TBFLAG_ANY,
+ * are stored in flags. The flags that are specific to a given mode
+ * are stores in flags2. Since cs_base is sized on the configured
+ * address size, flags2 always has 64-bits for A64, and a minimum of
+ * 32-bits for A32 and M32.
+ *
+ * The bits for 32-bit A-profile and M-profile partially overlap:
+ *
+ * 18 9 0
+ * +----------------+--------------+
+ * | TBFLAG_A32 | |
+ * +-----+----------+ TBFLAG_AM32 |
+ * | |TBFLAG_M32| |
+ * +-----+----------+--------------+
+ * 14 9 0
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
@@ -3342,19 +3349,19 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
#define DP_TBFLAG_ANY(DST, WHICH, VAL) \
(DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
#define DP_TBFLAG_A64(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A64, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL))
#define DP_TBFLAG_A32(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A32, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
#define DP_TBFLAG_M32(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_M32, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
#define DP_TBFLAG_AM32(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_AM32, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
-#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A64, WHICH)
-#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A32, WHICH)
-#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_M32, WHICH)
-#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_AM32, WHICH)
+#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH)
+#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
+#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
+#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
/**
* cpu_mmu_index:
diff --git a/target/arm/translate.h b/target/arm/translate.h
index f30287e554..50c2aba066 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -402,7 +402,7 @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64,
TCGArg, MemOp);
*/
static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
{
- return (CPUARMTBFlags){ tb->flags };
+ return (CPUARMTBFlags){ tb->flags, tb->cs_base };
}
/*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index cc73acc927..0d7c8817b6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13030,7 +13030,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
CPUARMTBFlags flags;
uint32_t pstate_for_ss;
- *cs_base = 0;
assert_hflags_rebuild_correctly(env);
flags = env->hflags;
@@ -13101,6 +13100,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
}
*pflags = flags.flags;
+ *cs_base = flags.flags2;
}
#ifdef TARGET_AARCH64
--
2.25.1
- [PATCH v3 00/30] target/arm: enforce alignment, Richard Henderson, 2021/01/11
- [PATCH v3 01/30] target/arm: Fix decode of align in VLDST_single, Richard Henderson, 2021/01/11
- [PATCH v3 02/30] target/arm: Rename TBFLAG_A32, SCTLR_B, Richard Henderson, 2021/01/11
- [PATCH v3 03/30] target/arm: Rename TBFLAG_ANY, PSTATE_SS, Richard Henderson, 2021/01/11
- [PATCH v3 04/30] target/arm: Add wrapper macros for accessing tbflags, Richard Henderson, 2021/01/11
- [PATCH v3 05/30] target/arm: Introduce CPUARMTBFlags, Richard Henderson, 2021/01/11
- [PATCH v3 06/30] target/arm: Move mode specific TB flags to tb->cs_base,
Richard Henderson <=
- [PATCH v3 07/30] target/arm: Move TBFLAG_AM32 bits to the top, Richard Henderson, 2021/01/11
- [PATCH v3 08/30] target/arm: Move TBFLAG_ANY bits to the bottom, Richard Henderson, 2021/01/11
- [PATCH v3 09/30] target/arm: Add ALIGN_MEM to TBFLAG_ANY, Richard Henderson, 2021/01/11
- [PATCH v3 12/30] target/arm: Fix SCTLR_B test for TCGv_i64 load/store, Richard Henderson, 2021/01/11
- [PATCH v3 13/30] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness, Richard Henderson, 2021/01/11
- [PATCH v3 11/30] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64, Richard Henderson, 2021/01/11
- [PATCH v3 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, Richard Henderson, 2021/01/11
- [PATCH v3 21/30] target/arm: Enforce alignment for VLDn (all lanes), Richard Henderson, 2021/01/11
- [PATCH v3 14/30] target/arm: Enforce word alignment for LDRD/STRD, Richard Henderson, 2021/01/11
- [PATCH v3 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness, Richard Henderson, 2021/01/11