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Re: [PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension
From: |
Rémi Denis-Courmont |
Subject: |
Re: [PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension |
Date: |
Wed, 13 Jan 2021 15:12:04 +0200 |
Le tiistaina 12. tammikuuta 2021, 23.30.39 EET Richard Henderson a écrit :
> On 1/12/21 12:45 AM, remi.denis.courmont@huawei.com wrote:
> > From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
> >
> > This adds handling for the SCR_EL3.EEL2 bit.
> >
> > Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
>
> The patch title seems to have gone awry.
>
> > @@ -2832,9 +2832,19 @@ static bool msr_banked_access_decode
> >
> > }
> > if (s->current_el == 1) {
> >
> > /* If we're in Secure EL1 (which implies that EL3 is AArch64)
> >
> > - * then accesses to Mon registers trap to EL3
> > + * then accesses to Mon registers trap to Secure EL2, if it
> > exists, + * otherwise EL3.
> >
> > */
> >
> > - TCGv_i32 tcg_el = tcg_const_i32(3);
> > + TCGv_i32 tcg_el;
> > +
> > + if (dc_isar_feature(aa64_sel2, s)) {
> > + /* Target EL is EL<3 minus SCR_EL3.EEL2> */
> > + tcg_el = load_cpu_field(cp15.scr_el3);
> > + tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1);
> > + tcg_gen_addi_i32(tcg_el, tcg_el, 3);
> > + } else {
> > + tcg_el = tcg_const_i32(3);
> > + }
>
> You can't test an aa64 feature without verifying that the cpu has aa64
> support (if the cpu is strictly aa32, the aa64 registers are
> undefined/uninitialized). So:
>
> if (arm_dc_feature(s, ARM_FEATURE_AARCH64) &&
> dc_isar_feature(aa64_sel2, s)) {
> ...
>
Hmm, yeah. Should this be an ifdef on TARGET_AARCH64 instead?
Also do we need to revector the exception code, or leave it mostly duplicated
as is?
> With those things changed,
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
>
> r~
--
Rémi Denis-Courmont
- [PATCH 09/19] target/arm: add ARMv8.4-SEL2 system registers, (continued)
- [PATCH 09/19] target/arm: add ARMv8.4-SEL2 system registers, remi . denis . courmont, 2021/01/12
- [PATCH 06/19] target/arm: declare new AA64PFR0 bit-fields, remi . denis . courmont, 2021/01/12
- [PATCH 03/19] target/arm: use arm_is_el2_enabled() where applicable, remi . denis . courmont, 2021/01/12
- [PATCH 11/19] target/arm: do S1_ptw_translate() before address space lookup, remi . denis . courmont, 2021/01/12
- [PATCH 14/19] target/arm: secure stage 2 translation regime, remi . denis . courmont, 2021/01/12
- [PATCH 12/19] target/arm: translate NS bit in page-walks, remi . denis . courmont, 2021/01/12
- [PATCH 07/19] target/arm: add 64-bit S-EL2 to EL exception table, remi . denis . courmont, 2021/01/12
- [PATCH 17/19] target/arm: add ARMv8.4-SEL2 extension, remi . denis . courmont, 2021/01/12
- [PATCH 13/19] target/arm: generalize 2-stage page-walk condition, remi . denis . courmont, 2021/01/12
- [PATCH 16/19] target/arm: revector to run-time pick target EL, remi . denis . courmont, 2021/01/12
- [PATCH 18/19] target/arm: enable Secure EL2 in max CPU, remi . denis . courmont, 2021/01/12
- [PATCH 19/19] target/arm: refactor vae1_tlbmask(), remi . denis . courmont, 2021/01/12
- [PATCH 15/19] target/arm: set HPFAR_EL2.NS on secure stage 2 faults, remi . denis . courmont, 2021/01/12
- Re: [PATCHv5 00/19] ARMv8.4-A Secure EL2, Peter Maydell, 2021/01/19