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[PULL 04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB
From: |
Alistair Francis |
Subject: |
[PULL 04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB |
Date: |
Sun, 17 Jan 2021 13:53:55 -0800 |
From: Atish Patra <atish.patra@wdc.com>
Currently, we place the DTB at 2MB from 4GB or end of DRAM which ever is
lesser. However, Linux kernel can address only 1GB of memory for RV32.
Thus, it can not map anything beyond 3GB (assuming 2GB is the starting address).
As a result, it can not process DT and panic if opensbi dynamic firmware
is used. While at it, place the DTB further away to avoid in memory placement
issues in future.
Fix this by placing the DTB at 16MB from 3GB or end of DRAM whichever is lower.
Fixes: 66b1205bc5ab ("RISC-V: Copy the fdt in dram instead of ROM")
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Message-id: 20210107091127.3407870-1-atish.patra@wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/boot.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 83586aef41..10a601b4dc 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -194,11 +194,11 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t
mem_size, void *fdt)
/*
* We should put fdt as far as possible to avoid kernel/initrd overwriting
* its content. But it should be addressable by 32 bit system as well.
- * Thus, put it at an aligned address that less than fdt size from end of
- * dram or 4GB whichever is lesser.
+ * Thus, put it at an 16MB aligned address that less than fdt size from the
+ * end of dram or 3GB whichever is lesser.
*/
- temp = MIN(dram_end, 4096 * MiB);
- fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB);
+ temp = MIN(dram_end, 3072 * MiB);
+ fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB);
fdt_pack(fdt);
/* copy in the device tree */
--
2.29.2
- [PULL 00/12] riscv-to-apply queue, Alistair Francis, 2021/01/17
- [PULL 01/12] hw/block: m25p80: Don't write to flash if write is disabled, Alistair Francis, 2021/01/17
- [PULL 02/12] hw/block: m25p80: Implement AAI-WP command support for SST flashes, Alistair Francis, 2021/01/17
- [PULL 12/12] riscv: Pass RISCVHartArrayState by pointer, Alistair Francis, 2021/01/17
- [PULL 03/12] gdb: riscv: Add target description, Alistair Francis, 2021/01/17
- [PULL 06/12] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type, Alistair Francis, 2021/01/17
- [PULL 05/12] target/riscv/pmp: Raise exception if no PMP entry is configured, Alistair Francis, 2021/01/17
- [PULL 04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB,
Alistair Francis <=
- [PULL 09/12] target/riscv: Add CSR name in the CSR function table, Alistair Francis, 2021/01/17
- [PULL 07/12] hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite, Alistair Francis, 2021/01/17
- [PULL 10/12] target/riscv: Generate the GDB XML file for CSR registers dynamically, Alistair Francis, 2021/01/17
- [PULL 08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external, Alistair Francis, 2021/01/17
- [PULL 11/12] target/riscv: Remove built-in GDB XML files for CSRs, Alistair Francis, 2021/01/17
- Re: [PULL 00/12] riscv-to-apply queue, Peter Maydell, 2021/01/18