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[PULL 08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
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From: |
Alistair Francis |
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Subject: |
[PULL 08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external |
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Date: |
Sun, 17 Jan 2021 13:53:59 -0800 |
From: Bin Meng <bin.meng@windriver.com>
In preparation to generate the CSR register list for GDB stub
dynamically, change csr_ops[] to non-static so that it can be
referenced externally.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1610427124-49887-2-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 8 ++++++++
target/riscv/csr.c | 10 +---------
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6339e84819..464653d70d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -478,6 +478,14 @@ typedef struct {
riscv_csr_op_fn op;
} riscv_csr_operations;
+/* CSR function table constants */
+enum {
+ CSR_TABLE_SIZE = 0x1000
+};
+
+/* CSR function table */
+extern riscv_csr_operations csr_ops[];
+
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 10ab82ed1f..507e8ee763 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -23,14 +23,6 @@
#include "qemu/main-loop.h"
#include "exec/exec-all.h"
-/* CSR function table */
-static riscv_csr_operations csr_ops[];
-
-/* CSR function table constants */
-enum {
- CSR_TABLE_SIZE = 0x1000
-};
-
/* CSR function table public API */
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
{
@@ -1378,7 +1370,7 @@ int riscv_csrrw_debug(CPURISCVState *env, int csrno,
target_ulong *ret_value,
}
/* Control and Status Register function table */
-static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
+riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
/* User Floating-Point CSRs */
[CSR_FFLAGS] = { fs, read_fflags, write_fflags },
[CSR_FRM] = { fs, read_frm, write_frm },
--
2.29.2
- [PULL 01/12] hw/block: m25p80: Don't write to flash if write is disabled, (continued)
- [PULL 01/12] hw/block: m25p80: Don't write to flash if write is disabled, Alistair Francis, 2021/01/17
- [PULL 02/12] hw/block: m25p80: Implement AAI-WP command support for SST flashes, Alistair Francis, 2021/01/17
- [PULL 12/12] riscv: Pass RISCVHartArrayState by pointer, Alistair Francis, 2021/01/17
- [PULL 03/12] gdb: riscv: Add target description, Alistair Francis, 2021/01/17
- [PULL 06/12] hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type, Alistair Francis, 2021/01/17
- [PULL 05/12] target/riscv/pmp: Raise exception if no PMP entry is configured, Alistair Francis, 2021/01/17
- [PULL 04/12] RISC-V: Place DTB at 3GB boundary instead of 4GB, Alistair Francis, 2021/01/17
- [PULL 09/12] target/riscv: Add CSR name in the CSR function table, Alistair Francis, 2021/01/17
- [PULL 07/12] hw/misc/sifive_u_otp: handling the fails of blk_pread and blk_pwrite, Alistair Francis, 2021/01/17
- [PULL 10/12] target/riscv: Generate the GDB XML file for CSR registers dynamically, Alistair Francis, 2021/01/17
- [PULL 08/12] target/riscv: Make csr_ops[CSR_TABLE_SIZE] external,
Alistair Francis <=
- [PULL 11/12] target/riscv: Remove built-in GDB XML files for CSRs, Alistair Francis, 2021/01/17
- Re: [PULL 00/12] riscv-to-apply queue, Peter Maydell, 2021/01/18