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[PATCH v2 17/25] hw/sd: ssi-sd: Support multiple block write
From: |
Bin Meng |
Subject: |
[PATCH v2 17/25] hw/sd: ssi-sd: Support multiple block write |
Date: |
Sat, 23 Jan 2021 18:40:08 +0800 |
From: Bin Meng <bin.meng@windriver.com>
For a multiple block write operation, each block begins with a multi
write start token. Unlike the SD mode that the multiple block write
ends when receiving a STOP_TRAN command (CMD12), a special stop tran
token is used to signal the card.
Emulating this by manually sending a CMD12 to the SD card core, to
bring it out of the receiving data state.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v2:
- Correct the "token" typo in the commit message
- Introduce multiple write token definitions in this patch
hw/sd/ssi-sd.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
index 240cfd919c..ee4fbc3dfe 100644
--- a/hw/sd/ssi-sd.c
+++ b/hw/sd/ssi-sd.c
@@ -82,6 +82,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD)
#define SSI_SDR_ADDRESS_ERROR 0x2000
#define SSI_SDR_PARAMETER_ERROR 0x4000
+/* multiple block write */
+#define SSI_TOKEN_MULTI_WRITE 0xfc
+/* terminate multiple block write */
+#define SSI_TOKEN_STOP_TRAN 0xfd
/* single block read/write, multiple block read */
#define SSI_TOKEN_SINGLE 0xfe
@@ -94,6 +98,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD)
static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val)
{
ssi_sd_state *s = SSI_SD(dev);
+ SDRequest request;
+ uint8_t longresp[16];
/*
* Special case: allow CMD12 (STOP TRANSMISSION) while reading data.
@@ -125,9 +131,31 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev,
uint32_t val)
return SSI_DUMMY;
break;
case SSI_TOKEN_SINGLE:
+ case SSI_TOKEN_MULTI_WRITE:
DPRINTF("Start write block\n");
s->mode = SSI_SD_DATA_WRITE;
return SSI_DUMMY;
+ case SSI_TOKEN_STOP_TRAN:
+ DPRINTF("Stop multiple write\n");
+
+ /* manually issue cmd12 to stop the transfer */
+ request.cmd = 12;
+ request.arg = 0;
+ s->arglen = sdbus_do_command(&s->sdbus, &request, longresp);
+ if (s->arglen <= 0) {
+ s->arglen = 1;
+ /* a zero value indicates the card is busy */
+ s->response[0] = 0;
+ DPRINTF("SD card busy\n");
+ } else {
+ s->arglen = 1;
+ /* a non-zero value indicates the card is ready */
+ s->response[0] = SSI_DUMMY;
+ }
+
+ s->mode = SSI_SD_RESPONSE;
+ s->response_pos = 0;
+ return SSI_DUMMY;
}
s->cmd = val & 0x3f;
@@ -136,8 +164,6 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev,
uint32_t val)
return SSI_DUMMY;
case SSI_SD_CMDARG:
if (s->arglen == 4) {
- SDRequest request;
- uint8_t longresp[16];
/* FIXME: Check CRC. */
request.cmd = s->cmd;
request.arg = ldl_be_p(s->cmdarg);
--
2.25.1
- [PATCH v2 08/25] hw/sd: ssi-sd: Add a state representing Nac, (continued)
- [PATCH v2 08/25] hw/sd: ssi-sd: Add a state representing Nac, Bin Meng, 2021/01/23
- [PATCH v2 18/25] hw/sd: ssi-sd: Bump up version ids of VMStateDescription, Bin Meng, 2021/01/23
- [PATCH v2 13/25] hw/sd: sd: Allow single/multiple block write for SPI mode, Bin Meng, 2021/01/23
- [PATCH v2 14/25] hw/sd: sd.h: Cosmetic change of using spaces, Bin Meng, 2021/01/23
- [PATCH v2 15/25] hw/sd: Introduce receive_ready() callback, Bin Meng, 2021/01/23
- [PATCH v2 17/25] hw/sd: ssi-sd: Support multiple block write,
Bin Meng <=
- [PATCH v2 19/25] hw/ssi: Add SiFive SPI controller support, Bin Meng, 2021/01/23
- [PATCH v2 20/25] hw/riscv: sifive_u: Add QSPI0 controller and connect a flash, Bin Meng, 2021/01/23
- [PATCH v2 16/25] hw/sd: ssi-sd: Support single block write, Bin Meng, 2021/01/23
- [PATCH v2 24/25] docs/system: Add RISC-V documentation, Bin Meng, 2021/01/23
- [PATCH v2 23/25] docs/system: Sort targets in alphabetical order, Bin Meng, 2021/01/23
- [PATCH v2 21/25] hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card, Bin Meng, 2021/01/23
- [PATCH v2 22/25] hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value, Bin Meng, 2021/01/23
- [PATCH v2 25/25] docs/system: riscv: Add documentation for sifive_u machine, Bin Meng, 2021/01/23
- Re: [PATCH v2 00/25] hw/riscv: sifive_u: Add missing SPI support, Philippe Mathieu-Daudé, 2021/01/24