[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 6/7] ppc/pnv: Remove default disablement of the PNOR contents
From: |
David Gibson |
Subject: |
Re: [PATCH 6/7] ppc/pnv: Remove default disablement of the PNOR contents |
Date: |
Thu, 28 Jan 2021 11:52:42 +1100 |
On Tue, Jan 26, 2021 at 06:10:58PM +0100, Cédric Le Goater wrote:
> On PowerNV systems, the BMC is in charge of mapping the PNOR contents
> on the LPC FW address space using the HIOMAP protocol. Under QEMU, we
> emulate this behavior and we also add an extra control on the flash
> accesses by letting the HIOMAP command handler decide whether the
> memory region is accessible or not depending on the firmware requests.
>
> However, this behavior is not compatible with hostboot like firmwares
> which need this mapping to be always available. For this reason, the
> PNOR memory region is initially disabled for skiboot mode only.
>
> This is badly placed under the LPC model and requires the use of the
> machine. Since it doesn't add much, simply remove the initial setting.
> The extra control in the HIOMAP command handler will still be performed.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Applied to ppc-for-6.0, thanks.
> ---
> hw/ppc/pnv_lpc.c | 8 --------
> 1 file changed, 8 deletions(-)
>
> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
> index 590359022084..11739e397b27 100644
> --- a/hw/ppc/pnv_lpc.c
> +++ b/hw/ppc/pnv_lpc.c
> @@ -825,7 +825,6 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool
> use_cpld, Error **errp)
> qemu_irq *irqs;
> qemu_irq_handler handler;
> PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
> - bool hostboot_mode = !!pnv->fw_load_addr;
>
> /* let isa_bus_new() create its own bridge on SysBus otherwise
> * devices specified on the command line won't find the bus and
> @@ -856,13 +855,6 @@ ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool
> use_cpld, Error **errp)
> */
> memory_region_add_subregion(&lpc->isa_fw, PNOR_SPI_OFFSET,
> &pnv->pnor->mmio);
> - /*
> - * Start disabled. The HIOMAP protocol will activate the mapping
> - * with HIOMAP_C_CREATE_WRITE_WINDOW
> - */
> - if (!hostboot_mode) {
> - memory_region_set_enabled(&pnv->pnor->mmio, false);
> - }
>
> return isa_bus;
> }
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
signature.asc
Description: PGP signature
- Re: [PATCH 4/7] ppc/pnv: Simplify pnv_bmc_create(), (continued)
Re: [PATCH 4/7] ppc/pnv: Simplify pnv_bmc_create(), David Gibson, 2021/01/27
[PATCH 1/7] ppc/pnv: Add trace events for PCI event notification, Cédric Le Goater, 2021/01/26
[PATCH 7/7] ppc/pnv: Introduce a LPC FW memory region attribute to map the PNOR, Cédric Le Goater, 2021/01/26
[PATCH 6/7] ppc/pnv: Remove default disablement of the PNOR contents, Cédric Le Goater, 2021/01/26
[PATCH 3/7] ppc/pnv: Use skiboot addresses to load kernel and ramfs, Cédric Le Goater, 2021/01/26
Re: [PATCH 3/7] ppc/pnv: Use skiboot addresses to load kernel and ramfs, David Gibson, 2021/01/27