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Re: [PATCH v2 1/1] target/arm: Fix SCR RES1 handling
From: |
Richard Henderson |
Subject: |
Re: [PATCH v2 1/1] target/arm: Fix SCR RES1 handling |
Date: |
Wed, 3 Feb 2021 08:28:26 -1000 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 |
On 2/3/21 6:55 AM, michael.nawrocki--- via wrote:
> The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them
> to 1 only when there is no support for AArch32 at EL1 or above.
>
> The reset value will be 0x30 only if the CPU is AArch64-only; if there
> is support for AArch32 at EL1 or above, it will be reset to 0.
>
> Also adds helper function isar_feature_aa64_aa32_el1 to check if AArch32
> is supported at EL1 or above.
>
> Signed-off-by: Mike Nawrocki <michael.nawrocki@gtri.gatech.edu>
> ---
> target/arm/cpu.h | 5 +++++
> target/arm/helper.c | 16 ++++++++++++++--
> 2 files changed, 19 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~