[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructio
|
From: |
LIU Zhiwei |
|
Subject: |
[PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions |
|
Date: |
Fri, 12 Feb 2021 23:02:34 +0800 |
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 9 ++
target/riscv/insn32.decode | 9 ++
target/riscv/insn_trans/trans_rvp.c.inc | 44 ++++++++++
target/riscv/packed_helper.c | 109 ++++++++++++++++++++++++
4 files changed, 171 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 4dc66cf4cc..0bd21c8514 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1268,3 +1268,12 @@ DEF_HELPER_3(pkbb16, tl, env, tl, tl)
DEF_HELPER_3(pkbt16, tl, env, tl, tl)
DEF_HELPER_3(pktt16, tl, env, tl, tl)
DEF_HELPER_3(pktb16, tl, env, tl, tl)
+
+DEF_HELPER_3(smmul, tl, env, tl, tl)
+DEF_HELPER_3(smmul_u, tl, env, tl, tl)
+DEF_HELPER_4(kmmac, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmmac_u, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmmsb, tl, env, tl, tl, tl)
+DEF_HELPER_4(kmmsb_u, tl, env, tl, tl, tl)
+DEF_HELPER_3(kwmmul, tl, env, tl, tl)
+DEF_HELPER_3(kwmmul_u, tl, env, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index a4d9ff2282..e0be2790dc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -736,3 +736,12 @@ pkbb16 0000111 ..... ..... 001 ..... 1111111 @r
pkbt16 0001111 ..... ..... 001 ..... 1111111 @r
pktt16 0010111 ..... ..... 001 ..... 1111111 @r
pktb16 0011111 ..... ..... 001 ..... 1111111 @r
+
+smmul 0100000 ..... ..... 001 ..... 1111111 @r
+smmul_u 0101000 ..... ..... 001 ..... 1111111 @r
+kmmac 0110000 ..... ..... 001 ..... 1111111 @r
+kmmac_u 0111000 ..... ..... 001 ..... 1111111 @r
+kmmsb 0100001 ..... ..... 001 ..... 1111111 @r
+kmmsb_u 0101001 ..... ..... 001 ..... 1111111 @r
+kwmmul 0110001 ..... ..... 001 ..... 1111111 @r
+kwmmul_u 0111001 ..... ..... 001 ..... 1111111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index 99a19019eb..fbc9c0b57b 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -520,3 +520,47 @@ GEN_RVP_R_OOL(pkbb16);
GEN_RVP_R_OOL(pkbt16);
GEN_RVP_R_OOL(pktt16);
GEN_RVP_R_OOL(pktb16);
+
+/* Most Significant Word "32x32" Multiply & Add Instructions */
+GEN_RVP_R_OOL(smmul);
+GEN_RVP_R_OOL(smmul_u);
+
+/* Function to accumulate destination register */
+static inline bool r_acc_ool(DisasContext *ctx, arg_r *a,
+ void (* fn)(TCGv, TCGv_ptr, TCGv, TCGv, TCGv))
+{
+ TCGv src1, src2, src3, dst;
+ if (!has_ext(ctx, RVP)) {
+ return false;
+ }
+
+ src1 = tcg_temp_new();
+ src2 = tcg_temp_new();
+ src3 = tcg_temp_new();
+ dst = tcg_temp_new();
+
+ gen_get_gpr(src1, a->rs1);
+ gen_get_gpr(src2, a->rs2);
+ gen_get_gpr(src3, a->rd);
+ fn(dst, cpu_env, src1, src2, src3);
+ gen_set_gpr(a->rd, dst);
+
+ tcg_temp_free(src1);
+ tcg_temp_free(src2);
+ tcg_temp_free(src3);
+ tcg_temp_free(dst);
+ return true;
+}
+
+#define GEN_RVP_R_ACC_OOL(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_r *a) \
+{ \
+ return r_acc_ool(s, a, gen_helper_##NAME); \
+}
+
+GEN_RVP_R_ACC_OOL(kmmac);
+GEN_RVP_R_ACC_OOL(kmmac_u);
+GEN_RVP_R_ACC_OOL(kmmsb);
+GEN_RVP_R_ACC_OOL(kmmsb_u);
+GEN_RVP_R_OOL(kwmmul);
+GEN_RVP_R_OOL(kwmmul_u);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index fe1b48c86d..c1322d2fac 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -1368,3 +1368,112 @@ static inline void do_pktb16(CPURISCVState *env, void
*vd, void *va,
}
RVPR(pktb16, 2, 2);
+
+/* Most Significant Word "32x32" Multiply & Add Instructions */
+static inline void do_smmul(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd, *a = va, *b = vb;
+ d[i] = (int64_t)a[i] * b[i] >> 32;
+}
+
+RVPR(smmul, 1, 4);
+
+static inline void do_smmul_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd, *a = va, *b = vb;
+ d[i] = ((int64_t)a[i] * b[i] + (uint32_t)INT32_MIN) >> 32;
+}
+
+RVPR(smmul_u, 1, 4);
+
+typedef void PackedFn4i(CPURISCVState *, void *, void *,
+ void *, void *, uint8_t);
+
+static inline target_ulong
+rvpr_acc(CPURISCVState *env, target_ulong a,
+ target_ulong b, target_ulong c,
+ uint8_t step, uint8_t size, PackedFn4i *fn)
+{
+ int i, passes = sizeof(target_ulong) / size;
+ target_ulong result = 0;
+
+ for (i = 0; i < passes; i += step) {
+ fn(env, &result, &a, &b, &c, i);
+ }
+ return result;
+}
+
+#define RVPR_ACC(NAME, STEP, SIZE) \
+target_ulong HELPER(NAME)(CPURISCVState *env, target_ulong a, \
+ target_ulong b, target_ulong c) \
+{ \
+ return rvpr_acc(env, a, b, c, STEP, SIZE, (PackedFn4i *)do_##NAME);\
+}
+
+static inline void do_kmmac(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *a = va, *b = vb, *c = vc;
+ d[i] = sadd32(env, 0, ((int64_t)a[i] * b[i]) >> 32, c[i]);
+}
+
+RVPR_ACC(kmmac, 1, 4);
+
+static inline void do_kmmac_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *a = va, *b = vb, *c = vc;
+ d[i] = sadd32(env, 0, ((int64_t)a[i] * b[i] +
+ (uint32_t)INT32_MIN) >> 32, c[i]);
+}
+
+RVPR_ACC(kmmac_u, 1, 4);
+
+static inline void do_kmmsb(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *a = va, *b = vb, *c = vc;
+ d[i] = ssub32(env, 0, c[i], (int64_t)a[i] * b[i] >> 32);
+}
+
+RVPR_ACC(kmmsb, 1, 4);
+
+static inline void do_kmmsb_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int32_t *d = vd, *a = va, *b = vb, *c = vc;
+ d[i] = ssub32(env, 0, c[i], ((int64_t)a[i] * b[i] +
+ (uint32_t)INT32_MIN) >> 32);
+}
+
+RVPR_ACC(kmmsb_u, 1, 4);
+
+static inline void do_kwmmul(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd, *a = va, *b = vb;
+ if (a[i] == INT32_MIN && b[i] == INT32_MIN) {
+ env->vxsat = 0x1;
+ d[i] = INT32_MAX;
+ } else {
+ d[i] = (int64_t)a[i] * b[i] >> 31;
+ }
+}
+
+RVPR(kwmmul, 1, 4);
+
+static inline void do_kwmmul_u(CPURISCVState *env, void *vd, void *va,
+ void *vb, uint8_t i)
+{
+ int32_t *d = vd, *a = va, *b = vb;
+ if (a[i] == INT32_MIN && b[i] == INT32_MIN) {
+ env->vxsat = 0x1;
+ d[i] = INT32_MAX;
+ } else {
+ d[i] = ((int64_t)a[i] * b[i] + (1ull << 30)) >> 31;
+ }
+}
+
+RVPR(kwmmul_u, 1, 4);
--
2.17.1
- [PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions, (continued)
- [PATCH 07/38] target/riscv: SIMD 8-bit Shift Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 08/38] target/riscv: SIMD 16-bit Compare Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 09/38] target/riscv: SIMD 8-bit Compare Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 10/38] target/riscv: SIMD 16-bit Multiply Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 11/38] target/riscv: SIMD 8-bit Multiply Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 01/38] target/riscv: implementation-defined constant parameters, LIU Zhiwei, 2021/02/12
- [PATCH 12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 14/38] target/riscv: 8-bit Unpacking Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 15/38] target/riscv: 16-bit Packing Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions,
LIU Zhiwei <=
- [PATCH 17/38] target/riscv: Signed MSW 32x16 Multiply and Add Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 19/38] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 20/38] target/riscv: Partial-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 22/38] target/riscv: 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 23/38] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions, LIU Zhiwei, 2021/02/12
- [PATCH 26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions, LIU Zhiwei, 2021/02/12