Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation processors

[Pankaj Gupta]

Hi Babu,

> >> +        .features[FEAT_8000_0008_EBX] =
> >> +            CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
> >> +            CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
> >> +            CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
> >> +            CPUID_8000_0008_EBX_AMD_SSBD,
> >
> > Don't have SSBD flag exposed in default EPYC-Rome CPU configuration?
> > Is there any reason for this?
> > Or do we need to explicitly add it?
>
> I think we missed it when we added EPYC-Rome model. I was going to add it
> sometime soon. As you know users can still add it with "+ssbd" if required.

Thanks for clarifying. I also see CPUID_8000_0008_EBX_IBRS missing for Rome.
Will it be okay if we add them now for Rome?

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6a53446e6a..b495116545 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -4161,7 +4161,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .features[FEAT_8000_0008_EBX] =
             CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
             CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
-            CPUID_8000_0008_EBX_STIBP,
+            CPUID_8000_0008_EBX_STIBP | CPUID_8000_0008_EBX_IBRS |
+            CPUID_8000_0008_EBX_AMD_SSBD,
         .features[FEAT_7_0_EBX] =
             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |