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[PULL 088/102] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) even
From: |
Cédric Le Goater |
Subject: |
[PULL 088/102] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event |
Date: |
Wed, 15 Dec 2021 18:03:43 +0100 |
From: Daniel Henrique Barboza <danielhb413@gmail.com>
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time SPR_CTRL is written. A small tweak in
pmu_increment_insns() is then needed to only increment this event
if the thread has the run latch.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-8-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 4 ++++
target/ppc/spr_tcg.h | 1 +
target/ppc/cpu_init.c | 2 +-
target/ppc/power8-pmu.c | 27 ++++++++++++++++++++++++---
target/ppc/translate.c | 12 ++++++++++++
5 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 313b16f39273..b0473526ced0 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -303,6 +303,7 @@ typedef enum {
PMU_EVENT_INACTIVE,
PMU_EVENT_CYCLES,
PMU_EVENT_INSTRUCTIONS,
+ PMU_EVENT_INSN_RUN_LATCH,
} PMUEventType;
/*****************************************************************************/
@@ -388,6 +389,9 @@ typedef enum {
#define MMCR1_PMC4SEL_START 56
#define MMCR1_PMC4EVT_EXTR (64 - MMCR1_PMC4SEL_START - MMCR1_EVT_SIZE)
+/* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */
+#define CTRL_RUN PPC_BIT(63)
+
/* LPCR bits */
#define LPCR_VPM0 PPC_BIT(0)
#define LPCR_VPM1 PPC_BIT(1)
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h
index 1d6521eedc83..f98d97c0ba17 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_tcg.h
@@ -28,6 +28,7 @@ void spr_write_generic(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn);
void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn);
void spr_write_PMC(DisasContext *ctx, int sprn, int gprn);
+void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn);
void spr_read_xer(DisasContext *ctx, int gprn, int sprn);
void spr_write_xer(DisasContext *ctx, int sprn, int gprn);
void spr_read_lr(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index e865d368f237..06ef15cd9e4e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6182,7 +6182,7 @@ static void register_book3s_ctrl_sprs(CPUPPCState *env)
{
spr_register(env, SPR_CTRL, "SPR_CTRL",
SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, &spr_write_generic,
+ SPR_NOACCESS, &spr_write_CTRL,
0x00000000);
spr_register(env, SPR_UCTRL, "SPR_UCTRL",
&spr_read_ureg, SPR_NOACCESS,
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index e163ba564012..08d1902cd5d6 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -96,6 +96,15 @@ static PMUEventType pmc_get_event(CPUPPCState *env, int sprn)
evt_type = PMU_EVENT_CYCLES;
}
break;
+ case 0xFA:
+ /*
+ * PMC4SEL = 0xFA is the "instructions completed
+ * with run latch set" event.
+ */
+ if (sprn == SPR_POWER_PMC4) {
+ evt_type = PMU_EVENT_INSN_RUN_LATCH;
+ }
+ break;
case 0xFE:
/*
* PMC1SEL = 0xFE is the architected PowerISA v3.1
@@ -117,7 +126,8 @@ bool pmu_insn_cnt_enabled(CPUPPCState *env)
int sprn;
for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
- if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS) {
+ if (pmc_get_event(env, sprn) == PMU_EVENT_INSTRUCTIONS ||
+ pmc_get_event(env, sprn) == PMU_EVENT_INSN_RUN_LATCH) {
return true;
}
}
@@ -132,11 +142,22 @@ static bool pmu_increment_insns(CPUPPCState *env,
uint32_t num_insns)
/* PMC6 never counts instructions */
for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
- if (pmc_get_event(env, sprn) != PMU_EVENT_INSTRUCTIONS) {
+ PMUEventType evt_type = pmc_get_event(env, sprn);
+ bool insn_event = evt_type == PMU_EVENT_INSTRUCTIONS ||
+ evt_type == PMU_EVENT_INSN_RUN_LATCH;
+
+ if (pmc_is_inactive(env, sprn) || !insn_event) {
continue;
}
- env->spr[sprn] += num_insns;
+ if (evt_type == PMU_EVENT_INSTRUCTIONS) {
+ env->spr[sprn] += num_insns;
+ }
+
+ if (evt_type == PMU_EVENT_INSN_RUN_LATCH &&
+ env->spr[SPR_CTRL] & CTRL_RUN) {
+ env->spr[sprn] += num_insns;
+ }
if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL &&
pmc_has_overflow_enabled(env, sprn)) {
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 633b907058e4..68fbbf67ecb4 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -403,6 +403,18 @@ void spr_write_generic(DisasContext *ctx, int sprn, int
gprn)
spr_store_dump_spr(sprn);
}
+void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
+{
+ spr_write_generic(ctx, sprn, gprn);
+
+ /*
+ * SPR_CTRL writes must force a new translation block,
+ * allowing the PMU to calculate the run latch events with
+ * more accuracy.
+ */
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
+}
+
#if !defined(CONFIG_USER_ONLY)
void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
{
--
2.31.1
- [PULL 084/102] target/ppc: PMU: update counters on PMCs r/w, (continued)
- [PULL 084/102] target/ppc: PMU: update counters on PMCs r/w, Cédric Le Goater, 2021/12/15
- [PULL 086/102] target/ppc: enable PMU counter overflow with cycle events, Cédric Le Goater, 2021/12/15
- [PULL 085/102] target/ppc: PMU: update counters on MMCR1 write, Cédric Le Goater, 2021/12/15
- [PULL 080/102] Revert "target/ppc: Move SPR_DSISR setting to powerpc_excp", Cédric Le Goater, 2021/12/15
- [PULL 072/102] ppc/ppc405: Change default PLL values at reset, Cédric Le Goater, 2021/12/15
- [PULL 077/102] target/ppc: fix xscvqpdp register access, Cédric Le Goater, 2021/12/15
- [PULL 091/102] ppc/pnv: Use the chip class to check the index of PHB3 devices, Cédric Le Goater, 2021/12/15
- [PULL 079/102] target/ppc: Fix e6500 boot, Cédric Le Goater, 2021/12/15
- [PULL 099/102] ppc/pnv: Compute the PHB index from the PHB4 PEC model, Cédric Le Goater, 2021/12/15
- [PULL 097/102] ppc/pnv: Introduce a "chip" property under the PHB4 model, Cédric Le Goater, 2021/12/15
- [PULL 088/102] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event,
Cédric Le Goater <=
- [PULL 096/102] ppc/pnv: Introduce version and device_id class atributes for PHB4 devices, Cédric Le Goater, 2021/12/15
- [PULL 094/102] ppc/pnv: Use QOM hierarchy to scan PHB3 devices, Cédric Le Goater, 2021/12/15
- [PULL 090/102] ppc/pnv: Introduce a "chip" property under PHB3, Cédric Le Goater, 2021/12/15
- [PULL 089/102] PPC64/TCG: Implement 'rfebb' instruction, Cédric Le Goater, 2021/12/15
- [PULL 087/102] target/ppc: enable PMU instruction count, Cédric Le Goater, 2021/12/15
- [PULL 101/102] ppc/pnv: Move realize of PEC stacks under the PEC model, Cédric Le Goater, 2021/12/15
- [PULL 095/102] ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices, Cédric Le Goater, 2021/12/15
- [PULL 061/102] ppc/ppc405: Change kernel load address, Cédric Le Goater, 2021/12/15
- [PULL 081/102] target/ppc: do not silence SNaN in xscvspdpn, Cédric Le Goater, 2021/12/15
- [PULL 092/102] ppc/pnv: Drop the "num-phbs" property, Cédric Le Goater, 2021/12/15