[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 061/102] ppc/ppc405: Change kernel load address
From: |
Cédric Le Goater |
Subject: |
[PULL 061/102] ppc/ppc405: Change kernel load address |
Date: |
Wed, 15 Dec 2021 18:03:16 +0100 |
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=1000000\0"
"fdt_addr_r=1800000\0"
"ramdisk_addr_r=1900000\0"
The taihu is one of these boards, the ref405ep is not but we don't
have much information on it and both boards have a very similar
address space layout.
Also, if loaded at address 0, U-Boot will partially overwrite the
uImage because of a bug in get_ram_size() (U-Boot v2015.10) not
restoring properly the probed RAM contents and because the exception
vectors are installed in the same range. Finally, a gzipped kernel
image will be uncompressed at 0x0. These are all good reasons for not
mappping a kernel image at this address.
Change the kernel load address to match U-Boot expectations and fix
loading.
Cc: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20211202191446.1292125-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211206103712.1866296-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc405_boards.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c
index 972a7a4a3e5d..b4249f4626e6 100644
--- a/hw/ppc/ppc405_boards.c
+++ b/hw/ppc/ppc405_boards.c
@@ -45,7 +45,7 @@
#define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2 * MiB)
-#define KERNEL_LOAD_ADDR 0x00000000
+#define KERNEL_LOAD_ADDR 0x01000000
#define INITRD_LOAD_ADDR 0x01800000
#define USE_FLASH_BIOS
--
2.31.1
- [PULL 099/102] ppc/pnv: Compute the PHB index from the PHB4 PEC model, (continued)
- [PULL 099/102] ppc/pnv: Compute the PHB index from the PHB4 PEC model, Cédric Le Goater, 2021/12/15
- [PULL 097/102] ppc/pnv: Introduce a "chip" property under the PHB4 model, Cédric Le Goater, 2021/12/15
- [PULL 088/102] target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event, Cédric Le Goater, 2021/12/15
- [PULL 096/102] ppc/pnv: Introduce version and device_id class atributes for PHB4 devices, Cédric Le Goater, 2021/12/15
- [PULL 094/102] ppc/pnv: Use QOM hierarchy to scan PHB3 devices, Cédric Le Goater, 2021/12/15
- [PULL 090/102] ppc/pnv: Introduce a "chip" property under PHB3, Cédric Le Goater, 2021/12/15
- [PULL 089/102] PPC64/TCG: Implement 'rfebb' instruction, Cédric Le Goater, 2021/12/15
- [PULL 087/102] target/ppc: enable PMU instruction count, Cédric Le Goater, 2021/12/15
- [PULL 101/102] ppc/pnv: Move realize of PEC stacks under the PEC model, Cédric Le Goater, 2021/12/15
- [PULL 095/102] ppc/pnv: Introduce a num_pecs class attribute for PHB4 PEC devices, Cédric Le Goater, 2021/12/15
- [PULL 061/102] ppc/ppc405: Change kernel load address,
Cédric Le Goater <=
- [PULL 081/102] target/ppc: do not silence SNaN in xscvspdpn, Cédric Le Goater, 2021/12/15
- [PULL 092/102] ppc/pnv: Drop the "num-phbs" property, Cédric Le Goater, 2021/12/15
- [PULL 076/102] target/ppc: Move xs{max,min}[cj]dp to decodetree, Cédric Le Goater, 2021/12/15
- [PULL 083/102] target/ppc: PMU basic cycle count for pseries TCG, Cédric Le Goater, 2021/12/15
- [PULL 093/102] ppc/pnv: Move mapping of the PHB3 CQ regions under pnv_pbcq_realize(), Cédric Le Goater, 2021/12/15
- [PULL 100/102] ppc/pnv: Remove "system-memory" property from PHB4 PEC, Cédric Le Goater, 2021/12/15
- [PULL 102/102] ppc/pnv: Use QOM hierarchy to scan PEC PHB4 devices, Cédric Le Goater, 2021/12/15
- [PULL 098/102] ppc/pnv: Introduce a num_stack class attribute, Cédric Le Goater, 2021/12/15
- Re: [PULL 000/102] ppc queue, Richard Henderson, 2021/12/15