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[PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field
From: |
Alistair Francis |
Subject: |
[PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field |
Date: |
Mon, 20 Dec 2021 14:55:50 +1000 |
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-6-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 72a716c999..bb62da7549 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -409,6 +409,7 @@ typedef enum {
#define SSTATUS_UPIE 0x00000010
#define SSTATUS_SPIE 0x00000020
#define SSTATUS_SPP 0x00000100
+#define SSTATUS_VS 0x00000600
#define SSTATUS_FS 0x00006000
#define SSTATUS_XS 0x00018000
#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index bb500afdeb..83f4dbd824 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -463,7 +463,7 @@ static const target_ulong vs_delegable_excps =
DELEGABLE_EXCPS &
(1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
- SSTATUS_SUM | SSTATUS_MXR;
+ SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS;
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
static const target_ulong hip_writable_mask = MIP_VSSIP;
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP |
MIP_VSEIP;
--
2.31.1
- [PULL 03/88] target/riscv: zfh: half-precision convert and move, (continued)
- [PULL 03/88] target/riscv: zfh: half-precision convert and move, Alistair Francis, 2021/12/19
- [PULL 04/88] target/riscv: zfh: half-precision floating-point compare, Alistair Francis, 2021/12/19
- [PULL 05/88] target/riscv: zfh: half-precision floating-point classify, Alistair Francis, 2021/12/19
- [PULL 06/88] target/riscv: zfh: add Zfh cpu property, Alistair Francis, 2021/12/19
- [PULL 07/88] target/riscv: zfh: implement zfhmin extension, Alistair Francis, 2021/12/19
- [PULL 09/88] target/riscv: drop vector 0.7.1 and add 1.0 support, Alistair Francis, 2021/12/19
- [PULL 08/88] target/riscv: zfh: add Zfhmin cpu property, Alistair Francis, 2021/12/19
- [PULL 11/88] target/riscv: rvv-1.0: add mstatus VS field, Alistair Francis, 2021/12/19
- [PULL 12/88] target/riscv: rvv-1.0: set mstatus.SD bit if mstatus.VS is dirty, Alistair Francis, 2021/12/19
- [PULL 10/88] target/riscv: Use FIELD_EX32() to extract wd field, Alistair Francis, 2021/12/19
- [PULL 13/88] target/riscv: rvv-1.0: add sstatus VS field,
Alistair Francis <=
- [PULL 14/88] target/riscv: rvv-1.0: introduce writable misa.v field, Alistair Francis, 2021/12/19
- [PULL 15/88] target/riscv: rvv-1.0: add translation-time vector context status, Alistair Francis, 2021/12/19
- [PULL 17/88] target/riscv: rvv-1.0: add vcsr register, Alistair Francis, 2021/12/19
- [PULL 16/88] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers, Alistair Francis, 2021/12/19
- [PULL 18/88] target/riscv: rvv-1.0: add vlenb register, Alistair Francis, 2021/12/19
- [PULL 19/88] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers, Alistair Francis, 2021/12/19
- [PULL 21/88] target/riscv: rvv-1.0: add fractional LMUL, Alistair Francis, 2021/12/19
- [PULL 20/88] target/riscv: rvv-1.0: remove MLEN calculations, Alistair Francis, 2021/12/19
- [PULL 22/88] target/riscv: rvv-1.0: add VMA and VTA, Alistair Francis, 2021/12/19
- [PULL 23/88] target/riscv: rvv-1.0: update check functions, Alistair Francis, 2021/12/19