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[PULL 41/88] target/riscv: rvv-1.0: element index instruction
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From: |
Alistair Francis |
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Subject: |
[PULL 41/88] target/riscv: rvv-1.0: element index instruction |
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Date: |
Mon, 20 Dec 2021 14:56:18 +1000 |
From: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-34-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3ac5162aeb..ab274dcde1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -633,7 +633,7 @@ vmsbf_m 010100 . ..... 00001 010 ..... 1010111
@r2_vm
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
-vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
+vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
--
2.31.1
- [PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions, (continued)
- [PULL 32/88] target/riscv: rvv-1.0: load/store whole register instructions, Alistair Francis, 2021/12/19
- [PULL 33/88] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns, Alistair Francis, 2021/12/19
- [PULL 34/88] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation, Alistair Francis, 2021/12/19
- [PULL 35/88] target/riscv: rvv-1.0: floating-point square-root instruction, Alistair Francis, 2021/12/19
- [PULL 37/88] target/riscv: rvv-1.0: count population in mask instruction, Alistair Francis, 2021/12/19
- [PULL 38/88] target/riscv: rvv-1.0: find-first-set mask bit instruction, Alistair Francis, 2021/12/20
- [PULL 36/88] target/riscv: rvv-1.0: floating-point classify instructions, Alistair Francis, 2021/12/20
- [PULL 39/88] target/riscv: rvv-1.0: set-X-first mask bit instructions, Alistair Francis, 2021/12/20
- [PULL 40/88] target/riscv: rvv-1.0: iota instruction, Alistair Francis, 2021/12/20
- [PULL 42/88] target/riscv: rvv-1.0: allow load element with sign-extended, Alistair Francis, 2021/12/20
- [PULL 41/88] target/riscv: rvv-1.0: element index instruction,
Alistair Francis <=
- [PULL 45/88] target/riscv: rvv-1.0: floating-point move instruction, Alistair Francis, 2021/12/20
- [PULL 46/88] target/riscv: rvv-1.0: floating-point scalar move instructions, Alistair Francis, 2021/12/20
- [PULL 44/88] target/riscv: rvv-1.0: integer scalar move instructions, Alistair Francis, 2021/12/20
- [PULL 47/88] target/riscv: rvv-1.0: whole register move instructions, Alistair Francis, 2021/12/20
- [PULL 49/88] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, Alistair Francis, 2021/12/20
- [PULL 50/88] target/riscv: rvv-1.0: single-width bit shift instructions, Alistair Francis, 2021/12/20
- [PULL 53/88] target/riscv: rvv-1.0: widening integer multiply-add instructions, Alistair Francis, 2021/12/20
- [PULL 54/88] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, Alistair Francis, 2021/12/20
- [PULL 51/88] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, Alistair Francis, 2021/12/20
- [PULL 52/88] target/riscv: rvv-1.0: narrowing integer right shift instructions, Alistair Francis, 2021/12/20