On 12/23/21 1:51 AM, Jasper Ruehl wrote:
Dear QEMU Community,
after chatting a bit in the IRC channel, "stefanha" advised me to
contact you via EMail about my problem.
My advisor and me from the DSE chair at the TU Munich had the idea to
improve the emulation of the x86 cmpxchg instruction on ARM64 CPUs by
improving the translation scheme: instead of generating a call to the
GCC helper function, we introduce a new TCG IR instruction (CAS) and
directly translate that into the ARM casal instruction.
If this is intended to ever be more than a class exercise,
there are a number of things that will have to be fixed:
- Host vs guest address size differences.
This affects, to begin, the number of arguments to the CAS opcode.
- Host vs guest address space mapping.
For system mode, this must go through the softmmu tlb.
For user-only mode, this must take guest_base into account.
- Host vs guest address alignment.
The x86_64 guest allows cmpxchg at odd addresses,
the aarch64 host requires cas at aligned addresses.
- Host isa support -- CASAL requires ARMv8.1 FEAT_LSE.
For ARMv8.0, you would want to emit an LDAXR/STLXR loop.
- No changes to target/ are required or desired.
The tcg_gen_atomic_cmpxchg_{i32,i64}() functions
are the interface that should be modified.
case INDEX_op_cas8:
case INDEX_op_cas16:
case INDEX_op_cas32:
case INDEX_op_cas64:
return C_O1_I3(r,r,r,r);
Your constraints are incorrect. For the CASAL instruction, the cmp
input (1) must match the old output (0). This would have to be
"r,0,r,r".
r~