Re: [Qemu-ppc] [Qemu-devel] [PATCH 2/5] target-ppc: USE LPCR_ILE to control exception endian on POWER7

[Andreas Färber]

Am 07.08.2013 02:47, schrieb Anton Blanchard:
> On POWER7, LPCR_ILE is used to control what endian guests take
> their exceptions in so use it instead of MSR_ILE.
> 
> Signed-off-by: Anton Blanchard <address@hidden>
> ---
>  target-ppc/cpu.h         |  2 ++
>  target-ppc/excp_helper.c | 10 ++++++++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 711db08..422a6bb 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -453,6 +453,8 @@ struct ppc_slb_t {
>  #define MSR_RI   1  /* Recoverable interrupt                        1        
> */
>  #define MSR_LE   0  /* Little-endian mode                           1 hflags 
> */
>  
> +#define LPCR_ILE (1 << (63-38))
> +
>  #define msr_sf   ((env->msr >> MSR_SF)   & 1)
>  #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
>  #define msr_shv  ((env->msr >> MSR_SHV)  & 1)
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index e9fcad8..e957761 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -611,9 +611,19 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int 
> excp_model, int excp)
>          tlb_flush(env, 1);
>      }
>  
> +#ifdef TARGET_PPC64
> +    if (excp_model == POWERPC_EXCP_POWER7) {
> +        if (env->spr[SPR_LPCR] & LPCR_ILE) {
> +            new_msr |= (target_ulong)1 << MSR_LE;
> +        }
> +    } else if (msr_ile) {
> +        new_msr |= (target_ulong)1 << MSR_LE;
> +    }
> +#else

You could just do

...
    } else
#endif

to spare duplicating the msr_ile path.

Andreas

>      if (msr_ile) {
>          new_msr |= (target_ulong)1 << MSR_LE;
>      }
> +#endif
>  
>      /* Jump to handler */
>      vector = env->excp_vectors[excp];
> 


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