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[Qemu-ppc] [PULL 10/50] target/ppc: SDR1 is a hypervisor resource
From: |
David Gibson |
Subject: |
[Qemu-ppc] [PULL 10/50] target/ppc: SDR1 is a hypervisor resource |
Date: |
Wed, 1 Mar 2017 15:43:25 +1100 |
At present the SDR1 register - the base of the system's hashed page table
(HPT) - is represented as an SPR with supervisor read and write permission.
However, on CPUs which have a hypervisor mode, the SDR1 is a hypervisor
only resource. Change the permission checking on the SPR to reflect this.
Now that this is done, we don't need to check for an external HPT executing
mtsdr1: an external HPT only applies when we're emulating the behaviour of
a hypervisor, rather than modelling the CPU's hypervisor mode internally,
so if we're permitted to execute mtsdr1, we don't have an external HPT.
Signed-off-by: David Gibson <address@hidden>
Reviewed-by: Suraj Jitindar Singh <address@hidden>
---
target/ppc/misc_helper.c | 8 +++-----
target/ppc/translate_init.c | 20 ++++++++++++++++----
2 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index ab432ba..fa573dd 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -82,11 +82,9 @@ void helper_store_sdr1(CPUPPCState *env, target_ulong val)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
- if (!env->external_htab) {
- if (env->spr[SPR_SDR1] != val) {
- ppc_store_sdr1(env, val);
- tlb_flush(CPU(cpu));
- }
+ if (env->spr[SPR_SDR1] != val) {
+ ppc_store_sdr1(env, val);
+ tlb_flush(CPU(cpu));
}
}
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index a1405e9..c92435d 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -740,10 +740,22 @@ static void gen_spr_ne_601 (CPUPPCState *env)
&spr_read_decr, &spr_write_decr,
0x00000000);
/* Memory management */
- spr_register(env, SPR_SDR1, "SDR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_sdr1,
- 0x00000000);
+#ifndef CONFIG_USER_ONLY
+ if (env->has_hv_mode) {
+ /* SDR1 is a hypervisor resource on CPUs which have a
+ * hypervisor mode */
+ spr_register_hv(env, SPR_SDR1, "SDR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_sdr1,
+ 0x00000000);
+ } else {
+ spr_register(env, SPR_SDR1, "SDR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_sdr1,
+ 0x00000000);
+ }
+#endif
}
/* BATs 0-3 */
--
2.9.3
- [Qemu-ppc] [PULL 00/50] ppc-for-2.9 queue 20170301, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 01/50] target/ppc: move cpu_[read, write]_xer to cpu.c, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 05/50] target/ppc: introduce helper_update_ov_legacy, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 02/50] target/ppc: optimize gen_write_xer(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 06/50] sysemu: support up to 1024 vCPUs, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 10/50] target/ppc: SDR1 is a hypervisor resource,
David Gibson <=
- [Qemu-ppc] [PULL 18/50] target/ppc: update ca32 in arithmetic substract, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 09/50] target/ppc: Merge cpu_ppc_set_vhyp() with cpu_ppc_set_papr(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 19/50] target/ppc: update overflow flags for add/sub, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 14/50] target/ppc: Remove the function ppc_hash64_set_sdr1(), David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 03/50] PCI: add missing classes in pci_ids.h to build device tree, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 20/50] target/ppc: use tcg ops for neg instruction, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 04/50] spapr: generate DT node names, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 16/50] target/ppc: support for 32-bit carry and overflow, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 17/50] target/ppc: update ca32 in arithmetic add, David Gibson, 2017/02/28
- [Qemu-ppc] [PULL 15/50] target/ppc: Correct SDR1 masking, David Gibson, 2017/02/28