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[PULL 18/18] target/ppc: fix vector registers access in gdbstub for litt
From: |
David Gibson |
Subject: |
[PULL 18/18] target/ppc: fix vector registers access in gdbstub for little-endian |
Date: |
Fri, 27 Aug 2021 17:09:46 +1000 |
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
As vector registers are stored in host endianness, we shouldn't swap its
64-bit elements in user mode. Add a 16-byte case in
ppc_maybe_bswap_register to handle the reordering of elements in softmmu
and remove avr_need_swap which is now unused.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210826145656.2507213-3-matheus.ferst@eldorado.org.br>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/gdbstub.c | 32 +++++++-------------------------
1 file changed, 7 insertions(+), 25 deletions(-)
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 09ff1328d4..1808a150e4 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -101,6 +101,8 @@ void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t
*mem_buf, int len)
bswap32s((uint32_t *)mem_buf);
} else if (len == 8) {
bswap64s((uint64_t *)mem_buf);
+ } else if (len == 16) {
+ bswap128s((Int128 *)mem_buf);
} else {
g_assert_not_reached();
}
@@ -389,15 +391,6 @@ const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const
char *xml_name)
}
#endif
-static bool avr_need_swap(CPUPPCState *env)
-{
-#ifdef HOST_WORDS_BIGENDIAN
- return msr_le;
-#else
- return !msr_le;
-#endif
-}
-
#if !defined(CONFIG_USER_ONLY)
static int gdb_find_spr_idx(CPUPPCState *env, int n)
{
@@ -486,14 +479,9 @@ static int gdb_get_avr_reg(CPUPPCState *env, GByteArray
*buf, int n)
if (n < 32) {
ppc_avr_t *avr = cpu_avr_ptr(env, n);
- if (!avr_need_swap(env)) {
- gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]);
- } else {
- gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]);
- }
+ gdb_get_reg128(buf, avr->VsrD(0), avr->VsrD(1));
mem_buf = gdb_get_reg_ptr(buf, 16);
- ppc_maybe_bswap_register(env, mem_buf, 8);
- ppc_maybe_bswap_register(env, mem_buf + 8, 8);
+ ppc_maybe_bswap_register(env, mem_buf, 16);
return 16;
}
if (n == 32) {
@@ -515,15 +503,9 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t
*mem_buf, int n)
{
if (n < 32) {
ppc_avr_t *avr = cpu_avr_ptr(env, n);
- ppc_maybe_bswap_register(env, mem_buf, 8);
- ppc_maybe_bswap_register(env, mem_buf + 8, 8);
- if (!avr_need_swap(env)) {
- avr->u64[0] = ldq_p(mem_buf);
- avr->u64[1] = ldq_p(mem_buf + 8);
- } else {
- avr->u64[1] = ldq_p(mem_buf);
- avr->u64[0] = ldq_p(mem_buf + 8);
- }
+ ppc_maybe_bswap_register(env, mem_buf, 16);
+ avr->VsrD(0) = ldq_p(mem_buf);
+ avr->VsrD(1) = ldq_p(mem_buf + 8);
return 16;
}
if (n == 32) {
--
2.31.1
- [PULL 08/18] ppc/pnv: Change the POWER10 machine to support DD2 only, (continued)
- [PULL 08/18] ppc/pnv: Change the POWER10 machine to support DD2 only, David Gibson, 2021/08/27
- [PULL 10/18] ppc/pnv: Use a simple incrementing index for the chip-id, David Gibson, 2021/08/27
- [PULL 13/18] ppc/xive: Export PQ get/set routines, David Gibson, 2021/08/27
- [PULL 12/18] ppc/pnv: add a chip topology index for POWER10, David Gibson, 2021/08/27
- [PULL 11/18] ppc/pnv: Distribute RAM among the chips, David Gibson, 2021/08/27
- [PULL 06/18] ppc/pnv: update skiboot to commit 820d43c0a775., David Gibson, 2021/08/27
- [PULL 17/18] include/qemu/int128.h: introduce bswap128s, David Gibson, 2021/08/27
- [PULL 14/18] ppc/xive: Export xive_presenter_notify(), David Gibson, 2021/08/27
- [PULL 15/18] include/qemu/int128.h: define struct Int128 according to the host endianness, David Gibson, 2021/08/27
- [PULL 16/18] target/ppc: fix vextu[bhw][lr]x helpers, David Gibson, 2021/08/27
- [PULL 18/18] target/ppc: fix vector registers access in gdbstub for little-endian,
David Gibson <=
- Re: [PULL 00/18] ppc-for-6.2 queue 20210827, Peter Maydell, 2021/08/28