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Re: OpenMPIC controller emulation in qemu ?

From: Andrew Randrianasulu
Subject: Re: OpenMPIC controller emulation in qemu ?
Date: Thu, 16 May 2024 04:33:10 +0300


чт, 16 мая 2024 г., 03:57 Andrew Randrianasulu <randrianasulu@gmail.com>:


чт, 16 мая 2024 г., 01:59 Andrew Randrianasulu <randrianasulu@gmail.com>:


On Thu, May 16, 2024 at 1:33 AM BALATON Zoltan <balaton@eik.bme.hu> wrote:
On Thu, 16 May 2024, Andrew Randrianasulu wrote:
> On Wed, May 15, 2024 at 5:09 PM Andrew Randrianasulu <
> randrianasulu@gmail.com> wrote:
>
>> I was researching why SMP was disabled in NewWorld mac99 machine in qeumu
>>
>> There was request some time ago about SMP support ...
>>
>> https://mail.gnu.org/archive/html/qemu-devel/2023-12/msg00907.html
>>
>> anyway i digged around a bit and found evidence both freeBSD and openBSD
>> supported SMP on real G4 Macs ...
>>
>> https://svnweb.freebsd.org/base?view=revision&revision=209767
>>
>> http://www.undeadly.org/cgi?action="">
>>
>> and linux at least in 3.x days
>>
>> https://ubuntuforums.org/archive/index.php/t-1947450.html
>> ====
>> # cat /proc/cpuinfo
>> processor : 0
>> cpu : 7400, altivec supported
>> temperature : 31-33 C (uncalibrated)
>> clock : 500.000000MHz
>> revision : 2.9 (pvr 000c 0209)
>> bogomips : 49.81
>>
>> processor : 1
>> cpu : 7400, altivec supported
>> temperature : 27-29 C (uncalibrated)
>> clock : 500.000000MHz
>> revision : 2.9 (pvr 000c 0209)
>> bogomips : 49.81
>>
>> total bogomips : 99.63
>> timebase : 24907667
>> platform : PowerMac
>> model : PowerMac3,3
>> machine : PowerMac3,3
>> motherboard : PowerMac3,3 MacRISC2 MacRISC Power Macintosh
>> detected as : 65 (PowerMac G4 AGP Graphics)
>> pmac flags : 00000014
>> L2 cache : 1024K unified
>> pmac-generation : NewWorld
>> Memory : 1536 MB
>> =====
>>
>> so i looked into Linux src
>>
>>
>> https://elixir.bootlin.com/linux/latest/source/arch/powerpc/platforms/powermac/pic.c
>>
>> https://elixir.bootlin.com/linux/latest/source/arch/powerpc/platforms/powermac/smp.c
>>
>>
>> may be I misread some lines but i think it says while timebase freezing
>> normally done   via gpio device there IS software fallback?
>> ====
>>
>> /* * SMP G4 use a GPIO to enable/disable the timebase. */
>> static unsigned int core99_tb_gpio <https://elixir.bootlin.com/linux/latest/C/ident/core99_tb_gpio>; /* Timebase freeze GPIO */
>> static void smp_core99_gpio_tb_freeze <https://elixir.bootlin.com/linux/latest/C/ident/smp_core99_gpio_tb_freeze>(int freeze <https://elixir.bootlin.com/linux/latest/C/ident/freeze>)
>>
>>
>> "static void __init
>> <https://elixir.bootlin.com/linux/latest/C/ident/__init>
>> smp_core99_setup_i2c_hwsync
>> <https://elixir.bootlin.com/linux/latest/C/ident/smp_core99_setup_i2c_hwsync>
>> (int ncpus <https://elixir.bootlin.com/linux/latest/C/ident/ncpus>)"
>>
>> - i2c was for g5/64 bit CPUs / systems ...
>>
>> ====
>>
>> also, apparently two MPICs can be cascaded for > 64 iIRQs ...but is it the
>> case on ANY smp-capable  powermac3.x ?
>>
>> There is github source of darwin driver from Apply, but it all c++ ..
>>
>>
>> https://github.com/apple-oss-distributions/AppleMPIC/blob/AppleMPIC-1.0/AppleMPIC.cpp
>>
>> So .. if anyone know any details about what else (apart from nr_cpu
>> property on openpic controller) might be missing  for smp emulation - I can
>> try your ideas :) on  MacOS 10.4.11 and Debian 8.1 virtual  installs ...
>>
>
>
> So I hacked it a bit just to see what broke
>
> bash-5.1$ diff -u  ~/botva/src/src/qemu/hw/ppc/mac_newworld.c
> hw/ppc/mac_newworld.c
> --- /home/guest/botva/src/src/qemu/hw/ppc/mac_newworld.c        2024-03-27
> 06:44:12.068828324 +0300
> +++ hw/ppc/mac_newworld.c       2024-05-16 00:53:26.345222034 +0300
> @@ -368,9 +368,13 @@
>     qdev_prop_set_chr(dev, "chrA", serial_hd(0));
>     qdev_prop_set_chr(dev, "chrB", serial_hd(1));
>
> +pic_dev = DEVICE(object_resolve_path_component(macio, "pic"));
> +    qdev_prop_set_uint32(pic_dev, "nb_cpus", machine->smp.cpus);
> +
> +
>     pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal);
>
> -    pic_dev = DEVICE(object_resolve_path_component(macio, "pic"));
> +
>     for (i = 0; i < 4; i++) {
>         qdev_connect_gpio_out(uninorth_pci_dev, i,
>                               qdev_get_gpio_in(pic_dev, 0x1b + i));
> @@ -575,7 +579,7 @@
>     mc->init = ppc_core99_init;
>     mc->block_default_type = IF_IDE;
>     /* SMP is not supported currently */
> -    mc->max_cpus = 1;
> +    mc->max_cpus = 2;
>     mc->default_boot_order = "cd";
>     mc->default_display = "std";
>     mc->default_nic = "sungem";
>
> and
>
> bash-5.1$ diff -u  ~/botva/src/src/qemu/hw/intc/openpic.c  hw/intc/openpic.c
> --- /home/guest/botva/src/src/qemu/hw/intc/openpic.c    2024-01-06
> 05:14:26.186344157 +0300
> +++ hw/intc/openpic.c   2024-05-16 00:58:14.489226704 +0300
> @@ -1584,8 +1584,8 @@
>         opp->mpic_mode_mask = GCR_MODE_MIXED;
>
>         if (opp->nb_cpus != 1) {
> -            error_setg(errp, "Only UP supported today");
> -            return;
> +            //error_setg(errp, "Only UP supported today");
> +            //return;

This is probably not enough, there might be some other things it needs to
do to support more than 1 CPU which is missing so maybe that's why it's
disabled. But I don't know what parts would that be and documentation of
this chip might not be easily available as it's some Apple part specific
to Macs which aren't well documented.

>         }
>
>         map_list(opp, list_le, &list_count);
>
>
> and openfirmware starts ....
>
> bash-5.1$ build/qemu-system-ppc -M mac99 -smp 2 -nographic
>
>>> =============================================================
>>> OpenBIOS 1.1 [Mar 7 2023 22:21]
>>> Configuration device id QEMU version 1 machine id 1
>>> CPUs: 2
>>> Memory: 128M
>>> UUID: 00000000-0000-0000-0000-000000000000
>>> CPU type PowerPC,G4
> milliseconds isn't unique.
> Welcome to OpenBIOS v1.1 built on Mar 7 2023 22:21
> Trying hd:,\\:tbxi...
> Trying hd:,\ppc\bootinfo.txt...
> Trying hd:,%BOOT...
> No valid state has been set by load or init-program
>
> 0 >
>
>
>
> but boooting finnix fails:
>
> bash-5.1$ build/qemu-system-ppc -M mac99 -smp 2 -nographic -cdrom
> ~/finnix-ppc-110.iso -boot d
>
>>> =============================================================
>>> OpenBIOS 1.1 [Mar 7 2023 22:21]
>>> Configuration device id QEMU version 1 machine id 1
>>> CPUs: 2
>>> Memory: 128M
>>> UUID: 00000000-0000-0000-0000-000000000000
>>> CPU type PowerPC,G4
> milliseconds isn't unique.
> Welcome to OpenBIOS v1.1 built on Mar 7 2023 22:21
> Trying cd:,\\:tbxi...
>>> switching to new context:
>
> я:interpret: exception -13 caught

There's a comment in openbios/forth/system/ciface.fs that says it might
not be an error and also a line:

\ ." INTERPRETE: --- " 2dup type

where you could remove the \ to get it print the Forth code that causes
the error. (By the way is INTERPRETE a typo with extra E at the end?)

> =====
>
> so any idea how I should extend this Keylargo controller ? :)

If you find docs then check what's missing otherwise you may need to find
that information out from open source drivers that set up the chip for
SMP. At least enable DEBUG_OPENPIC in the beginning of
qemu/hw/intc/openpic.c and run the QEMU comamnd with -d unimp.guest_errors
to get some more info on what is happening, that may point to some missing
parts.

it completely flush out OpenFrmware messages :/

but at least i can see  bunch of

qemu-system-ppc: info: Core-1: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core-1: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core-1: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core-1: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core-1: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core-1: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core-1: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core-1: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core-1: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 25 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core-1: openpic: set irq 25 = 0 ivpr=0xa0000000

but at the end it stuck at

qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
Eqemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
Xqemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
Iqemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
Tqemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000

qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
0qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
 qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
>qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
 qemu-system-ppc: info: Core0: openpic: set irq 37 = 0 ivpr=0xa0000000
QEMU: Terminated

oh, I just realized it printed EXIT but not in one line but over few lines! cool ....

sometimes it printed EXIT instead of "-13" ...so ... may be printing debug info slowed it down enough for avoiding this hang

found some more info (?) on openpic


it lists (hopefully) all important registers? but then at the moment of writing it was not very obvious how it was supposed to be viewed on pci systems?

time to download gdb,I guess ....

Also comment from netBSD:

./sys/arch/macppc/macppc/interrupts.c

====
/*
 * look for supported interrupt controllers                     
* there are several possible cases:                      
* - Ohare and Grand Central models have the same interrupt controller, Ohare                      
 *   can have a 2nd cascaded one ( Powerbook 3400c with ethernet for example )                     
 * - Heathrow is more or less Ohare with all the registers doubled to allow 64                      
*   IRQs 
* - openpic covers all OpenPICs built into various mac-io found in some G3,                       
 *   all G4 and most G5 models               
* - u3_ht is an OpenPIC built into the CPC 9x5 bridges / memory controllers                        
*   found in G5s, it's got enough quirks to require its own driver. Some                         
  *   models have both openpic and u3_ht, on those openpic handles IPIs and                         
 *   normal IRQs while the u3_ht is cascaded and can be used for MSI. On G5s                        
*   that have no openpic the u3_ht handles all interrupts, IPIs and MSI
=== end of quotation ====


there is document at

http://datasheet.datasheetarchive.com/originals/library/Datasheets-SW3/DSASW0048084.pdf

CPC945 Bridge and Memory Controller User Manual

this is big thing with MSIs and PCIe and Hypertransport and ...
 
I look at p. 286 currently where it describes interrupt controller ...

9.5.3 Registers Only a general description on the MPIC registers is provided here. For MPIC register details, see Section 12.6 MPIC Registers on page 359.

but this device not exactly openpic, there are differencies. I found few more pdfs but not looked into them yet.





 

Regards,
BALATON Zoltan
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