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qemu-riscv (date)
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Last Modified: Thu Jun 30 2022 02:18:26 -0400
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June 30, 2022
Re: [PATCH v9 0/2] QEMU RISC-V nested virtualization fixes
,
Anup Patel
,
02:18
[PATCH v9 2/2] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
02:12
[PATCH v9 1/2] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
02:12
[PATCH v9 0/2] QEMU RISC-V nested virtualization fixes
,
Anup Patel
,
02:12
June 29, 2022
Re: [PATCH 0/2] AIA draft v0.3.0 support for QEMU RISC-V
,
Alistair Francis
,
20:47
Re: [PATCH 2/2] target/riscv: Update default priority table for local interrupts
,
Alistair Francis
,
19:41
Re: [PATCH 1/2] target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
,
Alistair Francis
,
19:38
Re: [RFC PATCH v3] RISC-V: Add Zawrs ISA extension support
,
Alistair Francis
,
19:36
[PATCH 0/2] target/riscv: Fixes for Ibex and OpenTitan
,
Alistair Francis
,
19:31
[PATCH 2/2] target/riscv: Ibex: Support priv version 1.11
,
Alistair Francis
,
19:31
[PATCH 1/2] target/riscv: Fixup MSECCFG minimum priv check
,
Alistair Francis
,
19:31
Re: [PATCH v8 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
dramforever
,
08:14
Re: [PATCH v2] target/riscv: fix user-mode build issue because mhartid
,
Anup Patel
,
00:31
June 28, 2022
Re: [PATCH v2] target/riscv: fix user-mode build issue because mhartid
,
Bin Meng
,
23:53
Re: [PATCH v2] target/riscv: fix user-mode build issue because mhartid
,
Rahul Pathak
,
22:07
Re: [PATCH v2] target/riscv: fix user-mode build issue because mhartid
,
Alistair Francis
,
22:02
Re: [PATCH v8 2/4] target/riscv: Set minumum priv spec version for mcountinhibit
,
Alistair Francis
,
18:13
[PATCH v8 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
06:18
[PATCH v8 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
06:18
[PATCH v8 2/4] target/riscv: Set minumum priv spec version for mcountinhibit
,
Anup Patel
,
06:18
[PATCH v8 0/4] QEMU RISC-V nested virtualization fixes
,
Anup Patel
,
06:18
[PATCH v8 1/4] Revert "target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher"
,
Anup Patel
,
06:18
Re: [PATCH v6 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
05:58
[PATCH v7 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
00:41
[PATCH v7 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
00:41
[PATCH v7 2/4] target/riscv: Set minumum priv spec version for mcountinhibit
,
Anup Patel
,
00:40
[PATCH v7 1/4] Revert "target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher"
,
Anup Patel
,
00:40
[PATCH v7 0/4] QEMU RISC-V nested virtualization fixes
,
Anup Patel
,
00:40
June 27, 2022
Re: [PATCH v6 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
23:45
Re: [PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
23:43
Re: [PATCH] hw/riscv: boot: Reduce FDT address alignment constraints
,
Alistair Francis
,
19:24
Re: [PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Alistair Francis
,
19:19
Re: [PATCH v6 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Alistair Francis
,
19:17
Re: [PATCH v2] target/riscv: fix user-mode build issue because mhartid
,
Rahul Pathak
,
13:02
Re: [PATCH v6 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
dramforever
,
12:55
[PATCH v2] target/riscv: fix user-mode build issue because mhartid
,
Rahul Pathak
,
12:50
[PATCH v2] target/riscv: fix user-mode build issue because mhartid
,
Rahul Pathak
,
12:41
Re: [PATCH] target/riscv: fix user-mode build issue because mhartid
,
Rahul Pathak
,
12:01
Re: [PATCH v3 1/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
11:56
Re: [PATCH] target/riscv: fix user-mode build issue because mhartid
,
Víctor Colombo
,
10:46
Re: [PATCH] target/riscv: fix user-mode build issue because mhartid
,
Bin Meng
,
10:29
Re: [PATCH] hw/riscv: boot: Reduce FDT address alignment constraints
,
Bin Meng
,
10:03
[PATCH] target/riscv: fix user-mode build issue because mhartid
,
Rahul Pathak
,
05:40
Re: [RFC PATCH v3] RISC-V: Add Zawrs ISA extension support
,
Christoph Müllner
,
04:16
Re: [PATCH] hw/riscv: boot: Reduce FDT address alignment constraints
,
Atish Patra
,
03:01
Re: [RFC PATCH v3] RISC-V: Add Zawrs ISA extension support
,
Alistair Francis
,
01:20
Re: [PATCH v3 1/1] target/riscv: Add Zihintpause support
,
Alistair Francis
,
01:13
June 26, 2022
Re: [PATCH v6 0/4] QEMU RISC-V nested virtualization fixes
,
Alistair Francis
,
22:57
Re: [PATCH v6 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Alistair Francis
,
21:03
Re: [PATCH v6 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Alistair Francis
,
21:01
Re: [PATCH] hw/riscv: boot: Reduce FDT address alignment constraints
,
Alistair Francis
,
20:50
June 23, 2022
Re: [RFC PATCH v3] RISC-V: Add Zawrs ISA extension support
,
Heiko Stübner
,
12:37
[RFC PATCH v3] RISC-V: Add Zawrs ISA extension support
,
Christoph Muellner
,
11:29
Re: [PATCH] hw/riscv: boot: Reduce FDT address alignment constraints
,
Atish Kumar Patra
,
01:45
Re: [PATCH] hw/riscv: boot: Reduce FDT address alignment constraints
,
Alistair Francis
,
00:15
June 22, 2022
Re: [PATCH 4/4] hw/riscv: use qemu_fdt_setprop_strings() in sifive_u.c
,
Alistair Francis
,
01:14
June 21, 2022
Re: [PATCH v3 1/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
12:17
Re: [PATCH 4/4] hw/riscv: use qemu_fdt_setprop_strings() in sifive_u.c
,
Ben Dooks
,
06:54
June 20, 2022
Re: [PATCH v3 1/1] target/riscv: Add Zihintpause support
,
Alistair Francis
,
19:39
[PATCH v10 11/12] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
19:17
[PATCH v10 10/12] target/riscv: Add few cache related PMU events
,
Atish Patra
,
19:16
[PATCH v10 08/12] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
19:16
[PATCH v10 06/12] target/riscv: Add support for hpmcounters/hpmevents
,
Atish Patra
,
19:16
[PATCH v10 12/12] target/riscv: Update the privilege field for sscofpmf CSRs
,
Atish Patra
,
19:16
[PATCH v10 07/12] target/riscv: Support mcycle/minstret write operation
,
Atish Patra
,
19:16
[PATCH v10 03/12] target/riscv: pmu: Rename the counters extension to pmu
,
Atish Patra
,
19:16
[PATCH v10 09/12] target/riscv: Simplify counter predicate function
,
Atish Patra
,
19:16
[PATCH v10 05/12] target/riscv: Implement mcountinhibit CSR
,
Atish Patra
,
19:16
[PATCH v10 04/12] target/riscv: pmu: Make number of counters configurable
,
Atish Patra
,
19:16
[PATCH v10 00/12] Improve PMU support
,
Atish Patra
,
19:16
[PATCH v10 02/12] target/riscv: Implement PMU CSR predicate function for S-mode
,
Atish Patra
,
19:16
[PATCH v10 01/12] target/riscv: Fix PMU CSR predicate function
,
Atish Patra
,
19:16
[PATCH qemu v6 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions
,
~eopxd
,
02:51
[PATCH qemu v6 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions
,
~eopxd
,
02:51
[PATCH qemu v6 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
,
~eopxd
,
02:51
[PATCH qemu v6 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions
,
~eopxd
,
02:51
[PATCH qemu v6 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
02:51
[PATCH qemu v6 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior
,
~eopxd
,
02:51
[PATCH qemu v6 00/10] Add mask agnostic behavior for rvv instructions
,
~eopxd
,
02:51
[PATCH qemu v6 01/10] target/riscv: rvv: Add mask agnostic for vv instructions
,
~eopxd
,
02:51
[PATCH qemu v6 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
,
~eopxd
,
02:51
[PATCH qemu v6 03/10] target/riscv: rvv: Add mask agnostic for vx instructions
,
~eopxd
,
02:51
[PATCH qemu v6 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
,
~eopxd
,
02:51
Re: [PATCH 4/4] hw/riscv: use qemu_fdt_setprop_strings() in sifive_u.c
,
Alistair Francis
,
02:48
Re: [PATCH 3/4] device_tree: add qemu_fdt_setprop_strings() helper
,
Alistair Francis
,
02:47
Re: [PATCH 2/4] hw/riscv: use qemu_fdt_setprop_reg64_map() in sifive_u.c
,
Alistair Francis
,
02:44
Re: [PATCH 2/4] hw/riscv: use qemu_fdt_setprop_reg64_map() in sifive_u.c
,
Alistair Francis
,
02:43
Re: [PATCH 1/4] device_tree: add qemu_fdt_setprop_reg64_map helper
,
Alistair Francis
,
02:42
June 18, 2022
[PATCH 1/4] device_tree: add qemu_fdt_setprop_reg64_map helper
,
Ben Dooks
,
16:14
[PATCH 3/4] device_tree: add qemu_fdt_setprop_strings() helper
,
Ben Dooks
,
16:14
[PATCH 4/4] hw/riscv: use qemu_fdt_setprop_strings() in sifive_u.c
,
Ben Dooks
,
16:14
[v2] pair of device-tree helpers
,
Ben Dooks
,
16:14
[PATCH 2/4] hw/riscv: use qemu_fdt_setprop_reg64_map() in sifive_u.c
,
Ben Dooks
,
16:14
Re: [PATCH 4/4] hw/riscv: use qemu_fdt_setprop_strings() in sifive_u.c
,
Ben Dooks
,
15:40
June 17, 2022
[PATCH] include/hw/riscv: QOMify shakti_c
,
Vijai Kumar K
,
17:53
[PATCH] include/hw/char: QOMify shakti_uart
,
Vijai Kumar K
,
17:26
June 16, 2022
Re: [PATCH] target/riscv/pmp: guard against PMP ranges with a negative size
,
Alistair Francis
,
20:05
Re: [PATCH] target/riscv/pmp: guard against PMP ranges with a negative size
,
Alistair Francis
,
18:30
Re: [PATCH] target/riscv/pmp: guard against PMP ranges with a negative size
,
Nicolas Pitre
,
08:20
Re: [RFC PATCH v5 4/4] target/riscv: smstateen check for AIA/IMSIC
,
Alistair Francis
,
03:19
Re: [RFC PATCH v5 3/4] target/riscv: smstateen check for fcsr
,
Alistair Francis
,
03:17
Re: [RFC PATCH v5 2/4] target/riscv: smstateen check for h/senvcfg
,
Alistair Francis
,
03:01
Re: [RFC PATCH v5 2/4] target/riscv: smstateen check for h/senvcfg
,
Alistair Francis
,
02:56
Re: [RFC PATCH v5 2/4] target/riscv: smstateen check for h/senvcfg
,
Alistair Francis
,
02:54
Re: [RFC PATCH v5 1/4] target/riscv: Add smstateen support
,
Alistair Francis
,
01:49
Re: [PATCH] target/riscv/pmp: guard against PMP ranges with a negative size
,
Alistair Francis
,
01:04
June 15, 2022
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
,
Anup Patel
,
23:25
[PATCH 1/2] target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits
,
Anup Patel
,
23:17
[PATCH 2/2] target/riscv: Update default priority table for local interrupts
,
Anup Patel
,
23:17
[PATCH 0/2] AIA draft v0.3.0 support for QEMU RISC-V
,
Anup Patel
,
23:17
Re: [PATCH 1/3] target/riscv: Remove the redundant initialization of env->misa_mxl
,
Bin Meng
,
22:42
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
,
Alistair Francis
,
22:38
Re: [PATCH 1/3] target/riscv: Remove the redundant initialization of env->misa_mxl
,
Alistair Francis
,
22:34
[PATCH] target/riscv/pmp: guard against PMP ranges with a negative size
,
Nicolas Pitre
,
17:12
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
,
Atish Kumar Patra
,
14:21
Re: [PATCH] target/riscv: Update tval for hardware watchpoint
,
Richard Henderson
,
11:15
Re: [PATCH 9/9] target/riscv: debug: Add initial support of type 6 trigger
,
Bin Meng
,
09:18
Re: [PATCH 8/9] target/riscv: debug: Return 0 if previous value written to tselect >= number of triggers
,
Bin Meng
,
09:17
Re: [PATCH 7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger
,
Bin Meng
,
08:44
Re: [PATCH 6/9] target/riscv: debug: Create common trigger actions function
,
Bin Meng
,
08:42
Re: [PATCH 5/9] target/riscv: debug: Introduce tinfo CSR
,
Bin Meng
,
08:27
Re: [PATCH 4/9] target/riscv: debug: Restrict the range of tselect value can be written
,
Bin Meng
,
08:21
Re: [PATCH 3/9] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
,
Bin Meng
,
08:18
Re: [PATCH 2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content
,
Bin Meng
,
08:05
Re: [PATCH 1/9] target/riscv: debug: Determine the trigger type from tdata1.type
,
Bin Meng
,
01:41
Re: [PATCH 1/9] target/riscv: debug: Determine the trigger type from tdata1.type
,
Bin Meng
,
01:33
[PATCH] target/riscv: Update tval for hardware watchpoint
,
Bin Meng
,
00:08
June 13, 2022
Re: [PATCH 1/3] target/riscv: Remove the redundant initialization of env->misa_mxl
,
Bin Meng
,
08:30
June 12, 2022
Re: [PATCH 3/3] target/riscv: Skip parsing extensions from properties for KVM
,
Alistair Francis
,
20:36
Re: [PATCH 2/3] target/riscv: kvm: Set env->misa_ext_mask to the supported value
,
Alistair Francis
,
20:34
Re: [PATCH 1/3] target/riscv: Remove the redundant initialization of env->misa_mxl
,
Alistair Francis
,
20:33
Re: [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui
,
Alistair Francis
,
20:29
Re: [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui
,
Alistair Francis
,
19:37
June 11, 2022
[PATCH v6 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
04:02
[PATCH v6 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
04:02
[PATCH v6 0/4] QEMU RISC-V nested virtualization fixes
,
Anup Patel
,
04:02
[PATCH v6 1/4] target/riscv: Don't force update priv spec version to latest
,
Anup Patel
,
04:02
[PATCH v6 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher
,
Anup Patel
,
04:02
June 10, 2022
Re: [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui
,
Richard Henderson
,
14:11
Re: [PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
13:28
[PATCH] target/riscv: Remove condition guarding register zero for auipc and lui
,
Víctor Colombo
,
12:58
Re: [PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
dramforever
,
08:55
Re: [PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
dramforever
,
07:50
Re: [PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
07:21
[PATCH 9/9] target/riscv: debug: Add initial support of type 6 trigger
,
frank . chang
,
01:14
[PATCH 7/9] target/riscv: debug: Check VU/VS modes for type 2 trigger
,
frank . chang
,
01:14
[PATCH 6/9] target/riscv: debug: Create common trigger actions function
,
frank . chang
,
01:14
[PATCH 5/9] target/riscv: debug: Introduce tinfo CSR
,
frank . chang
,
01:14
[PATCH 3/9] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
,
frank . chang
,
01:14
[PATCH 8/9] target/riscv: debug: Return 0 if previous value written to tselect >= number of triggers
,
frank . chang
,
01:14
[PATCH 1/9] target/riscv: debug: Determine the trigger type from tdata1.type
,
frank . chang
,
01:14
[PATCH 2/9] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content
,
frank . chang
,
01:14
[PATCH 4/9] target/riscv: debug: Restrict the range of tselect value can be written
,
frank . chang
,
01:14
[PATCH 0/9] Improve RISC-V Debug support
,
frank . chang
,
01:13
June 09, 2022
Re: [PATCH] target/riscv: trans_rvv: Avoid assert for RV32 and e64
,
Alistair Francis
,
19:43
Re: [PATCH v4 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
12:21
Re: [PATCH v4 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Richard Henderson
,
09:58
Re: [PATCH] target/riscv: trans_rvv: Avoid assert for RV32 and e64
,
Richard Henderson
,
09:53
Re: [PATCH v3] target/riscv: Don't expose the CPU properties on names CPUs
,
Alistair Francis
,
01:40
[PATCH v3 1/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
00:41
[PATCH v3 0/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
00:41
June 08, 2022
[PATCH v5 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
23:31
[PATCH v5 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
23:31
[PATCH v5 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher
,
Anup Patel
,
23:31
[PATCH v5 1/4] target/riscv: Don't force update priv spec version to latest
,
Anup Patel
,
23:31
[PATCH v5 0/4] QEMU RISC-V nested virtualization fixes
,
Anup Patel
,
23:31
Re: [PATCH v4 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
23:17
Re: [PATCH v4 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Bin Meng
,
21:33
Re: [PATCH v4 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher
,
Bin Meng
,
21:28
Re: [PATCH v4 1/4] target/riscv: Don't force update priv spec version to latest
,
Bin Meng
,
21:20
[PATCH 3/3] target/riscv: Skip parsing extensions from properties for KVM
,
Bin Meng
,
21:07
[PATCH 2/3] target/riscv: kvm: Set env->misa_ext_mask to the supported value
,
Bin Meng
,
21:07
[PATCH 1/3] target/riscv: Remove the redundant initialization of env->misa_mxl
,
Bin Meng
,
21:07
[PATCH] target/riscv: trans_rvv: Avoid assert for RV32 and e64
,
Alistair Francis
,
19:47
Re: [PATCH v3 1/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
14:27
Re: [PATCH v4 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Richard Henderson
,
12:53
[PATCH v4 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
12:15
[PATCH v4 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
12:15
[PATCH v4 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher
,
Anup Patel
,
12:15
[PATCH v4 1/4] target/riscv: Don't force update priv spec version to latest
,
Anup Patel
,
12:15
[PATCH v4 0/4] QEMU RISC-V nested virtualization fixes
,
Anup Patel
,
12:15
Re: [PATCH 0/3] target/riscv: Fix issue 1060
,
Richard Henderson
,
11:32
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
,
Alistair Francis
,
03:19
Re: [PATCH] hw/riscv: boot: Reduce FDT address alignment constraints
,
Bin Meng
,
02:41
[PATCH] hw/riscv: boot: Reduce FDT address alignment constraints
,
Alistair Francis
,
02:20
[PATCH v3] target/riscv: Don't expose the CPU properties on names CPUs
,
Alistair Francis
,
02:15
June 07, 2022
[PATCH v3 1/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
23:45
[PATCH v3 0/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
23:45
Re: [PATCH v2] target/riscv: Don't expose the CPU properties on names CPUs
,
Alistair Francis
,
20:22
Re: [PATCH v2 1/1] target/riscv: Add Zihintpause support
,
Alistair Francis
,
20:04
Re: [PATCH v2] target/riscv: Don't expose the CPU properties on names CPUs
,
Bin Meng
,
19:27
Re: [PATCH v2 1/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
19:20
Re: [PATCH v2 1/1] target/riscv: Add Zihintpause support
,
Alistair Francis
,
19:04
Re: [PATCH v2] target/riscv: Don't expose the CPU properties on names CPUs
,
Alistair Francis
,
18:10
Re: [PATCH qemu v19 00/16] Add tail agnostic behavior for rvv instructions
,
Alistair Francis
,
17:45
Re: [PATCH v2 1/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
17:17
June 06, 2022
Re: [PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
23:05
Re: [PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Anup Patel
,
23:01
Re: [PATCH v3 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Anup Patel
,
22:51
Re: [PATCH] target/riscv/debug.c: keep experimental rv128 support working
,
Alistair Francis
,
03:26
[PATCH qemu v19 15/16] target/riscv: rvv: Add tail agnostic for vector permutation instructions
,
~eopxd
,
02:18
[PATCH qemu v19 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior
,
~eopxd
,
02:18
Re: [PATCH qemu v18 00/16] Add tail agnostic behavior for rvv instructions
,
eop Chen
,
02:18
[PATCH qemu v19 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions
,
~eopxd
,
02:18
[PATCH qemu v19 13/16] target/riscv: rvv: Add tail agnostic for vector reduction instructions
,
~eopxd
,
02:18
[PATCH qemu v19 10/16] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions
,
~eopxd
,
02:18
[PATCH qemu v19 07/16] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions
,
~eopxd
,
02:18
[PATCH qemu v19 14/16] target/riscv: rvv: Add tail agnostic for vector mask instructions
,
~eopxd
,
02:18
[PATCH qemu v19 08/16] target/riscv: rvv: Add tail agnostic for vector integer shift instructions
,
~eopxd
,
02:18
[PATCH qemu v19 04/16] target/riscv: rvv: Early exit when vstart >= vl
,
~eopxd
,
02:18
[PATCH qemu v19 02/16] target/riscv: rvv: Prune redundant access_type parameter passed
,
~eopxd
,
02:18
[PATCH qemu v19 01/16] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed
,
~eopxd
,
02:18
[PATCH qemu v19 12/16] target/riscv: rvv: Add tail agnostic for vector floating-point instructions
,
~eopxd
,
02:17
[PATCH qemu v19 11/16] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions
,
~eopxd
,
02:17
[PATCH qemu v19 05/16] target/riscv: rvv: Add tail agnostic for vv instructions
,
~eopxd
,
02:17
[PATCH qemu v19 00/16] Add tail agnostic behavior for rvv instructions
,
~eopxd
,
02:17
[PATCH qemu v19 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions
,
~eopxd
,
02:16
[PATCH qemu v19 03/16] target/riscv: rvv: Rename ambiguous esz
,
~eopxd
,
02:16
Re: [PATCH] target/riscv/debug.c: keep experimental rv128 support working
,
Bin Meng
,
02:09
Re: [PATCH] target/riscv/debug.c: keep experimental rv128 support working
,
Alistair Francis
,
02:04
Re: [PATCH v3 2/3] target/riscv: Make CPU property names lowercase
,
Alistair Francis
,
02:03
Re: [PATCH v3 1/3] target/riscv: Reorganize riscv_cpu_properties
,
Alistair Francis
,
02:03
Re: [PATCH] target/riscv: Wake on VS-level external interrupts
,
Alistair Francis
,
02:01
June 05, 2022
Re: [PATCH] target/riscv: Wake on VS-level external interrupts
,
Alistair Francis
,
22:55
Re: [PATCH v3 4/4] target/riscv: Force disable extensions if priv spec version does not match
,
Alistair Francis
,
21:55
Re: [PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Alistair Francis
,
21:54
Re: [PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Alistair Francis
,
21:49
Re: [PATCH qemu v18 00/16] Add tail agnostic behavior for rvv instructions
,
Alistair Francis
,
21:37
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
,
Atish Patra
,
12:23
June 03, 2022
[RFC PATCH v5 3/4] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
12:05
[RFC PATCH v5 1/4] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
12:05
[RFC PATCH v5 0/4] RISC-V Smstateen support
,
Mayuresh Chitale
,
12:05
[RFC PATCH v5 2/4] target/riscv: smstateen check for h/senvcfg
,
Mayuresh Chitale
,
12:05
[RFC PATCH v5 4/4] target/riscv: smstateen check for AIA/IMSIC
,
Mayuresh Chitale
,
12:04
[PATCH v3 1/3] target/riscv: Reorganize riscv_cpu_properties
,
Tsukasa OI
,
07:37
[PATCH v3 2/3] target/riscv: Make CPU property names lowercase
,
Tsukasa OI
,
07:37
[PATCH v3 0/3] target/riscv: Make CPU property names lowercase (w/ capitalized aliases)
,
Tsukasa OI
,
07:37
[PATCH v3 3/3] target/riscv: Deprecate capitalized property names
,
Tsukasa OI
,
07:37
June 02, 2022
Re: [RFC PATCH v2] RISC-V: Add Zawrs ISA extension support
,
Philipp Tomsich
,
11:57
[PATCH] target/riscv/debug.c: keep experimental rv128 support working
,
Frédéric Pétrot
,
11:54
Re: [RFC PATCH v2] RISC-V: Add Zawrs ISA extension support
,
Christoph Müllner
,
11:52
Re: [RFC PATCH v2] RISC-V: Add Zawrs ISA extension support
,
Richard Henderson
,
11:07
Re: [RFC PATCH v2] RISC-V: Add Zawrs ISA extension support
,
Heiko Stübner
,
10:34
[RFC PATCH v2] RISC-V: Add Zawrs ISA extension support
,
Christoph Muellner
,
09:40
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
,
Alistair Francis
,
02:59
June 01, 2022
Re: [PATCH v2 3/3] target/riscv: Deprecate capitalized property names
,
Alistair Francis
,
21:20
Re: [PATCH v2 2/3] target/riscv: Make CPU property names lowercase
,
Alistair Francis
,
21:18
Re: [PATCH] hw/intc: sifive_plic: Avoid overflowing the addr_config buffer
,
Alistair Francis
,
21:06
[RFC PATCH] RISC-V: Add Zawrs ISA extension support
,
Christoph Muellner
,
18:23
[RFC PATCH] RISC-V: Add Zawrs ISA extension support
,
Christoph Muellner
,
17:52
Re: [PATCH] hw/intc: sifive_plic: Avoid overflowing the addr_config buffer
,
Philippe Mathieu-Daudé
,
09:59
Re: [PATCH v2 1/3] target/riscv: Reorganize riscv_cpu_properties
,
Alistair Francis
,
00:05
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