Re: [PATCH v9 0/2] QEMU RISC-V nested virtualization fixes

[Alistair Francis]

On Thu, Jun 30, 2022 at 4:27 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Thu, Jun 30, 2022 at 11:42 AM Anup Patel <apatel@ventanamicro.com> wrote:
> >
> > This series does fixes and improvements to have nested virtualization
> > on QEMU RISC-V.
> >
> > These patches can also be found in riscv_nested_fixes_v9 branch at:
> > https://github.com/avpatel/qemu.git
> >
> > The RISC-V nested virtualization was tested on QEMU RISC-V using
> > Xvisor RISC-V which has required hypervisor support to run another
> > hypervisor as Guest/VM.
>
> Changes since v8:
>  - Drop first two patches because Alistair has already taken care of it.
>  - Include instruction immediate offset in "Addr. Offset" for PATCH1
>
> Regards,
> Anup
>
> >
> > Changes since v7:
> >  - Improve tinst "Addr. Offset" in PATCH3
> >
> > Changes since v6:
> >  - Droppred original PATCH1 and PATCH2 since these are already merged
> >  - Added PATCH1 to revert dummy mcountinhibit CSR
> >  - Added PATCH2 to fix minimum priv spec version for mcountinhibit CSR
> >  - Fixed checkpatch error in PATCH3
> >  - Fixed compile error in PATCH4
> >
> > Changes since v5:
> >  - Correctly set "Addr. Offset" for misaligned load/store traps in PATCH3
> >  - Use offsetof() instead of pointer in PATCH4
> >
> > Changes since v4:
> >  - Updated commit description in PATCH1, PATCH2, and PATCH4
> >  - Use "const" for local array in PATCH5
> >
> > Changes since v3:
> >  - Updated PATCH3 to set special pseudoinstructions in htinst for
> >    guest page faults which result due to VS-stage page table walks
> >  - Updated warning message in PATCH4
> >
> > Changes since v2:
> >  - Dropped the patch which are already in Alistair's next branch
> >  - Set "Addr. Offset" in the transformed instruction for PATCH3
> >  - Print warning in riscv_cpu_realize() if we are disabling an
> >    extension due to privilege spec verions mismatch for PATCH4
> >
> > Changes since v1:
> >  - Set write_gva to env->two_stage_lookup which ensures that for
> >    HS-mode to HS-mode trap write_gva is true only for HLV/HSV
> >    instructions
> >  - Included "[PATCH 0/3] QEMU RISC-V priv spec version fixes"
> >    patches in this series for easy review
> >  - Re-worked PATCH7 to force disable extensions if required
> >    priv spec version is not staisfied
> >  - Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine
> >
> > Anup Patel (2):
> >   target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
> >   target/riscv: Force disable extensions if priv spec version does not
> >     match
> >
> >  target/riscv/cpu.c        | 150 ++++++++++++++---------
> >  target/riscv/cpu.h        |   5 +
> >  target/riscv/cpu_helper.c | 252 +++++++++++++++++++++++++++++++++++++-
> >  target/riscv/instmap.h    |  45 +++++++
> >  4 files changed, 390 insertions(+), 62 deletions(-)

Thanks!

Applied to riscv-to-apply.next

Alistair

> >
> > --
> > 2.34.1
> >
>