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Re: [PATCH 1/6] target/riscv: add check for supported privilege modes co
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations |
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Date: |
Mon, 11 Jul 2022 15:29:06 +1000 |
On Sun, Jul 10, 2022 at 6:25 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> - There are 3 suggested privilege modes conbinations listed in the spec:
> 1) M, 2) M, U 3) M, S, U
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1bb3973806..0dad6906bc 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -636,6 +636,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> return;
> }
>
> + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) {
> + error_setg(errp,
> + "Setting S extension without U extension is illegal");
> + return;
> + }
> +
> if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
> error_setg(errp, "F extension requires Zicsr");
> return;
> --
> 2.17.1
>
>
- [PATCH 0/6] Improve the U/S/H extension related check, Weiwei Li, 2022/07/10
- [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations, Weiwei Li, 2022/07/10
- Re: [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations,
Alistair Francis <=
- [PATCH 5/6] target/riscv: fix checks in hmode/hmode32, Weiwei Li, 2022/07/10
- [PATCH 2/6] target/riscv: H extension depends on I extension, Weiwei Li, 2022/07/10
- [PATCH 4/6] target/riscv: add check for csrs existed with U extension, Weiwei Li, 2022/07/10
- [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check, Weiwei Li, 2022/07/10
- [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table, Weiwei Li, 2022/07/10