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Re: [PATCH v2 4/6] target/riscv: add check for csrs existed with U exten
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From: |
Andrew Jones |
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Subject: |
Re: [PATCH v2 4/6] target/riscv: add check for csrs existed with U extension |
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Date: |
Mon, 18 Jul 2022 11:49:53 +0200 |
On Tue, Jul 12, 2022 at 02:32:34PM +0800, Weiwei Li wrote:
> - add umode/umode32 predicate for mcounteren,menvcfg/menvcfgh
Same commit message and $SUBJECT comments as the other patches.
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/csr.c | 25 ++++++++++++++++++++++---
> 1 file changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 7d4b6ceced..1edeb69366 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -339,6 +339,25 @@ static RISCVException hmode32(CPURISCVState *env, int
> csrno)
>
> }
>
> +static RISCVException umode(CPURISCVState *env, int csrno)
> +{
> + if (riscv_has_ext(env, RVU)) {
> + /* User extension is supported */
This comment isn't very useful, riscv_has_ext(env, RVU) is
self-explanatory.
> + return RISCV_EXCP_NONE;
> + }
> +
> + return RISCV_EXCP_ILLEGAL_INST;
> +}
> +
> +static RISCVException umode32(CPURISCVState *env, int csrno)
> +{
> + if (riscv_cpu_mxl(env) != MXL_RV32) {
> + return RISCV_EXCP_ILLEGAL_INST;
> + }
> +
> + return umode(env, csrno);
> +}
> +
> /* Checks if PointerMasking registers could be accessed */
> static RISCVException pointer_masking(CPURISCVState *env, int csrno)
> {
> @@ -3519,7 +3538,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MEDELEG] = { "medeleg", any, read_medeleg, write_medeleg },
> [CSR_MIE] = { "mie", any, NULL, NULL, rmw_mie },
> [CSR_MTVEC] = { "mtvec", any, read_mtvec, write_mtvec },
> - [CSR_MCOUNTEREN] = { "mcounteren", any, read_mcounteren,
> + [CSR_MCOUNTEREN] = { "mcounteren", umode, read_mcounteren,
> write_mcounteren },
>
> [CSR_MSTATUSH] = { "mstatush", any32, read_mstatush,
> @@ -3553,9 +3572,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MIPH] = { "miph", aia_any32, NULL, NULL, rmw_miph },
>
> /* Execution environment configuration */
> - [CSR_MENVCFG] = { "menvcfg", any, read_menvcfg, write_menvcfg,
> + [CSR_MENVCFG] = { "menvcfg", umode, read_menvcfg, write_menvcfg,
> .min_priv_ver = PRIV_VERSION_1_12_0 },
> - [CSR_MENVCFGH] = { "menvcfgh", any32, read_menvcfgh, write_menvcfgh,
> + [CSR_MENVCFGH] = { "menvcfgh", umode32, read_menvcfgh, write_menvcfgh,
> .min_priv_ver = PRIV_VERSION_1_12_0 },
> [CSR_SENVCFG] = { "senvcfg", smode, read_senvcfg, write_senvcfg,
> .min_priv_ver = PRIV_VERSION_1_12_0 },
> --
> 2.17.1
>
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
- [PATCH v2 0/6] Improve the U/S/H extension related check, Weiwei Li, 2022/07/12
- [PATCH v2 5/6] target/riscv: fix checks in hmode/hmode32, Weiwei Li, 2022/07/12
- [PATCH v2 4/6] target/riscv: add check for csrs existed with U extension, Weiwei Li, 2022/07/12
- Re: [PATCH v2 4/6] target/riscv: add check for csrs existed with U extension,
Andrew Jones <=
- [PATCH v2 1/6] target/riscv: add check for supported privilege modes conbinations, Weiwei Li, 2022/07/12
- [PATCH v2 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table, Weiwei Li, 2022/07/12
- [PATCH v2 2/6] target/riscv: H extension depends on I extension, Weiwei Li, 2022/07/12
- [PATCH v2 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check, Weiwei Li, 2022/07/12