[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 4/8] target/riscv: debug: Restrict the range of tselect value
From: |
Bin Meng |
Subject: |
[PATCH v2 4/8] target/riscv: debug: Restrict the range of tselect value can be written |
Date: |
Fri, 9 Sep 2022 21:42:11 +0800 |
From: Frank Chang <frank.chang@sifive.com>
The value of tselect CSR can be written should be limited within the
range of supported triggers number.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
(no changes since v1)
target/riscv/debug.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 06feef7d67..d6666164cd 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -127,10 +127,6 @@ bool tdata_available(CPURISCVState *env, int tdata_index)
return false;
}
- if (unlikely(env->trigger_cur >= RV_MAX_TRIGGERS)) {
- return false;
- }
-
return tdata_mapping[trigger_type][tdata_index];
}
@@ -141,8 +137,9 @@ target_ulong tselect_csr_read(CPURISCVState *env)
void tselect_csr_write(CPURISCVState *env, target_ulong val)
{
- /* all target_ulong bits of tselect are implemented */
- env->trigger_cur = val;
+ if (val < RV_MAX_TRIGGERS) {
+ env->trigger_cur = val;
+ }
}
static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,
--
2.34.1
- [PATCH v2 0/8] target/riscv: Improve RISC-V Debug support, Bin Meng, 2022/09/09
- [PATCH v2 1/8] target/riscv: debug: Determine the trigger type from tdata1.type, Bin Meng, 2022/09/09
- [PATCH v2 2/8] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content, Bin Meng, 2022/09/09
- [PATCH v2 3/8] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs, Bin Meng, 2022/09/09
- [PATCH v2 4/8] target/riscv: debug: Restrict the range of tselect value can be written,
Bin Meng <=
- [PATCH v2 5/8] target/riscv: debug: Introduce tinfo CSR, Bin Meng, 2022/09/09
- [PATCH v2 6/8] target/riscv: debug: Create common trigger actions function, Bin Meng, 2022/09/09
- [PATCH v2 7/8] target/riscv: debug: Check VU/VS modes for type 2 trigger, Bin Meng, 2022/09/09
- [PATCH v2 8/8] target/riscv: debug: Add initial support of type 6 trigger, Bin Meng, 2022/09/09
- Re: [PATCH v2 0/8] target/riscv: Improve RISC-V Debug support, Alistair Francis, 2022/09/23