Re: Re: [PATCH v2] disas/riscv.c: rvv: Add disas support for vector instructions

[刘阳]

> -----Original Messages-----
&gt; From: "Alistair Francis" <alistair23@gmail.com>
&gt; Sent Time: 2022-09-27 09:57:39 (Tuesday)
&gt; To: "Yang Liu" <liuyang22@iscas.ac.cn>
&gt; Cc: "Palmer Dabbelt" <palmer@dabbelt.com>, "Alistair Francis" 
<alistair.francis@wdc.com>, "Bin Meng" <bin.meng@windriver.com>, "Tommy Wu" 
<tommy.wu@sifive.com>, "open list:RISC-V" <qemu-riscv@nongnu.org>, 
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>, wangjunqiang 
<wangjunqiang@iscas.ac.cn>, "Wei Wu (吴伟)" <lazyparser@gmail.com>, liweiwei 
<liweiwei@iscas.ac.cn>
&gt; Subject: Re: [PATCH v2] disas/riscv.c: rvv: Add disas support for vector 
instructions
&gt; 
&gt; On Fri, Sep 23, 2022 at 2:27 PM Alistair Francis <alistair23@gmail.com> 
wrote:
&gt; &gt;
&gt; &gt; On Fri, Aug 26, 2022 at 1:26 PM Yang Liu <liuyang22@iscas.ac.cn> 
wrote:
&gt; &gt; &gt;
&gt; &gt; &gt; Tested with https://github.com/ksco/rvv-decoder-tests
&gt; &gt; &gt;
&gt; &gt; &gt; Expected checkpatch errors for consistency and brevity reasons:
&gt; &gt; &gt;
&gt; &gt; &gt; ERROR: line over 90 characters
&gt; &gt; &gt; ERROR: trailing statements should be on next line
&gt; &gt; &gt; ERROR: braces {} are necessary for all arms of this statement
&gt; &gt; &gt;
&gt; &gt; &gt; Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn>
&gt; &gt;
&gt; &gt; Thanks!
&gt; &gt;
&gt; &gt; Applied to riscv-to-apply.next
&gt; 
&gt; This patch fails to build with this error:
&gt; 
&gt; ../disas/riscv.c: In function 'print_insn_riscv':
&gt; ../disas/riscv.c:4513:30: error: '__builtin___sprintf_chk' may write a
&gt; terminating nul past the end of the destination
&gt; [-Werror=format-overflow=]
&gt;  4513 |             sprintf(nbuf, "%d", sew);
&gt;       |                              ^
&gt; In file included from /usr/include/stdio.h:906,
&gt;                  from
&gt; 
/scratch/jenkins-tmp/workspace/QEMU-Multi-Config-Build/BUILD_OPTIONS/GCC/include/qemu/osdep.h:97,
&gt;                  from ../disas/riscv.c:20:
&gt; In function 'sprintf',
&gt;     inlined from 'format_inst' at ../disas/riscv.c:4513:13,
&gt;     inlined from 'disasm_inst' at ../disas/riscv.c:4640:5,
&gt;     inlined from 'print_insn_riscv' at ../disas/riscv.c:4690:5:
&gt; /usr/include/bits/stdio2.h:30:10: note: '__builtin___sprintf_chk'
&gt; output between 2 and 5 bytes into a destination of size 4
&gt;    30 |   return __builtin___sprintf_chk (__s, __USE_FORTIFY_LEVEL - 1,
&gt;       |          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
&gt;    31 |                                   __glibc_objsize (__s), __fmt,
&gt;       |                                   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
&gt;    32 |                                   __va_arg_pack ());
&gt;       |                                   ~~~~~~~~~~~~~~~~~
&gt; 
&gt; 
&gt; Alistair
&gt; 

Thanks for the review, I've submitted a v3 patch.

Yang

&gt; &gt; &gt;      decode_inst_operands(&amp;dec);
&gt; &gt; &gt;      decode_inst_decompress(&amp;dec, isa);
&gt; &gt; &gt;      decode_inst_lift_pseudo(&amp;dec);
&gt; &gt; &gt; -    format_inst(buf, buflen, 16, &amp;dec);
&gt; &gt; &gt; +    format_inst(buf, buflen, 24, &amp;dec);
&gt; &gt; &gt;  }
&gt; &gt; &gt;
&gt; &gt; &gt;  #define INST_FMT_2 "%04" PRIx64 "              "
&gt; &gt; &gt; --
&gt; &gt; &gt; 2.30.1 (Apple Git-130)
&gt; &gt; &gt;
&gt; &gt; &gt;
</liuyang22@iscas.ac.cn></liuyang22@iscas.ac.cn></alistair23@gmail.com></liweiwei@iscas.ac.cn></lazyparser@gmail.com></wangjunqiang@iscas.ac.cn></qemu-devel@nongnu.org></qemu-riscv@nongnu.org></tommy.wu@sifive.com></bin.meng@windriver.com></alistair.francis@wdc.com></palmer@dabbelt.com></liuyang22@iscas.ac.cn></alistair23@gmail.com>