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[PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEM
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From: |
Rajnesh Kanwal |
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Subject: |
[PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. |
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Date: |
Thu, 18 May 2023 12:38:34 +0100 |
RISCV_EXCP_SEMIHOST is set to 0x10, which can also be a local
interrupt as well. This change adds a check for async flag
before invoking semihosting logic.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 57d04385f1..c78a2a9514 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1602,7 +1602,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong htval = 0;
target_ulong mtval2 = 0;
- if (cause == RISCV_EXCP_SEMIHOST) {
+ if (!async && cause == RISCV_EXCP_SEMIHOST) {
do_common_semihosting(cs);
env->pc += 4;
return;
--
2.25.1
- [PATCH 0/6] Add RISC-V Virtual IRQs and IRQ filtering support, Rajnesh Kanwal, 2023/05/18
- [PATCH 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie., Rajnesh Kanwal, 2023/05/18
- [PATCH 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.,
Rajnesh Kanwal <=
- [PATCH 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip., Rajnesh Kanwal, 2023/05/18
- [PATCH 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled, Rajnesh Kanwal, 2023/05/18
- [PATCH 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support., Rajnesh Kanwal, 2023/05/18
- [PATCH 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support., Rajnesh Kanwal, 2023/05/18