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[PATCH 4/9] disas/riscv: Make rv_op_illegal a shared enum value
From: |
Christoph Muellner |
Subject: |
[PATCH 4/9] disas/riscv: Make rv_op_illegal a shared enum value |
Date: |
Tue, 30 May 2023 15:18:38 +0200 |
From: Christoph Müllner <christoph.muellner@vrull.eu>
The enum value 'rv_op_illegal' does not represent an
instruction, but is a catch-all value in case we have
no match in the decoder. Let's make the value a shared
one, so that other compile units can reuse it.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
disas/riscv.c | 2 +-
disas/riscv.h | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index a062fb48cc..4cf477bc02 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -22,7 +22,7 @@
#include "disas/riscv.h"
typedef enum {
- rv_op_illegal = 0,
+ /* 0 is reserved for rv_op_illegal. */
rv_op_lui = 1,
rv_op_auipc = 2,
rv_op_jal = 3,
diff --git a/disas/riscv.h b/disas/riscv.h
index 0f34b71518..de2623e3cc 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -189,6 +189,10 @@ typedef struct {
const rvc_constraint *constraints;
} rv_comp_data;
+enum {
+ rv_op_illegal = 0
+};
+
enum {
rvcd_imm_nz = 0x1
};
--
2.40.1
- [PATCH 0/9] disas/riscv: Add vendor extension support, Christoph Muellner, 2023/05/30
- [PATCH 1/9] target/riscv: Use xl instead of mxl for disassemble, Christoph Muellner, 2023/05/30
- [PATCH 2/9] target/riscv: Factor out RISCVCPUConfig from cpu.h, Christoph Muellner, 2023/05/30
- [PATCH 5/9] disas/riscv: Encapsulate opcode_data into decode, Christoph Muellner, 2023/05/30
- [PATCH 7/9] disas/riscv: Provide infrastructure for vendor extensions, Christoph Muellner, 2023/05/30
- [PATCH 8/9] disas/riscv: Add support for XVentanaCondOps, Christoph Muellner, 2023/05/30
- [PATCH 4/9] disas/riscv: Make rv_op_illegal a shared enum value,
Christoph Muellner <=
- [PATCH 9/9] disas/riscv: Add support for XThead* instructions, Christoph Muellner, 2023/05/30
- [PATCH 3/9] disas/riscv: Move types/constants to new header file, Christoph Muellner, 2023/05/30
- [PATCH 6/9] target/riscv/cpu: Share RISCVCPUConfig with disassembler, Christoph Muellner, 2023/05/30