Re: [PATCH v9 16/20] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext()

[Alistair Francis]

On Thu, Jul 6, 2023 at 8:20 PM Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
> riscv_isa_string_ext() is being used by riscv_isa_string(), which is
> then used by boards to retrieve the 'riscv,isa' string to be written in
> the FDT. All this happens after riscv_cpu_realize(), meaning that we're
> already past riscv_cpu_validate_set_extensions() and, more important,
> riscv_cpu_disable_priv_spec_isa_exts().
>
> This means that all extensions that needed to be disabled due to
> priv_spec mismatch are already disabled. Checking this again during
> riscv_isa_string_ext() is unneeded. Remove it.
>
> As a bonus, riscv_isa_string_ext() can now be used with the 'host'
> KVM-only CPU type since it doesn't have a env->priv_ver assigned and it
> would fail this check for no good reason.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index deb3c0f035..2acf77949f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -2124,8 +2124,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char 
> **isa_str,
>      int i;
>
>      for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
> -        if (cpu->env.priv_ver >= isa_edata_arr[i].min_version &&
> -            isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
> +        if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
>              new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
>              g_free(old);
>              old = new;
> --
> 2.41.0
>
>