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[RESEND PATCH v3 0/1] target/riscv: Add Zihintntl extension ISA string t
From: |
Jason Chien |
Subject: |
[RESEND PATCH v3 0/1] target/riscv: Add Zihintntl extension ISA string to DTS |
Date: |
Wed, 26 Jul 2023 07:40:45 +0000 |
In v2, I rebased the patch on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next
However, I forgot to add "Reviewed-by" in v2, so I add them in v3.
Jason Chien (1):
target/riscv: Add Zihintntl extension ISA string to DTS
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+)
--
2.17.1
- [RESEND PATCH v3 0/1] target/riscv: Add Zihintntl extension ISA string to DTS,
Jason Chien <=