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[RFC v1 4/8] Add enum with maximum ignored bits depending on privilege l
From: |
Alexey Baturo |
Subject: |
[RFC v1 4/8] Add enum with maximum ignored bits depending on privilege level for Zjpm v0.6.1 |
Date: |
Fri, 8 Sep 2023 18:26:36 +0000 |
Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
target/riscv/cpu.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 62dabfa207..25fe60476b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -88,6 +88,16 @@ typedef enum {
EXT_STATUS_DIRTY,
} RISCVExtStatus;
+/* Enum holds maximum for N bits to be ignored depending on privilege level */
+typedef enum {
+ PM_BARE_N_BITS = 16,
+ PM_SV32_N_BITS = 0,
+ PM_SV39_N_BITS = 25,
+ PM_SV48_N_BITS = 16,
+ PM_SV57_N_BITS = 7,
+ PM_SV64_N_BITS = 0,
+} RISCVZjpmMaxNBits;
+
#define MMU_USER_IDX 3
#define MAX_RISCV_PMPS (16)
--
2.34.1
- [RFC v1 0/8] RISC-V Pointer Masking update to Zjpm v0.6.1, Alexey Baturo, 2023/09/08
- [RFC v1 1/8] target/riscv: Remove obsolete pointer masking extension code, Alexey Baturo, 2023/09/08
- [RFC v1 2/8] target/riscv: Add new S{sn, mn, m}jpm extensions as part of Zjpm v0.6.1, Alexey Baturo, 2023/09/08
- [RFC v1 3/8] target/riscv: Add new bits in CSRs for Zjpm 0.6.1, Alexey Baturo, 2023/09/08
- [RFC v1 4/8] Add enum with maximum ignored bits depending on privilege level for Zjpm v0.6.1,
Alexey Baturo <=
- [RFC v1 5/8] target/riscv: Add pointer masking tb flags, Alexey Baturo, 2023/09/08
- [RFC v1 6/8] target/riscv: Add functions to calculate current N masked bits for pointer masking, Alexey Baturo, 2023/09/08
- [RFC v1 8/8] target/riscv: enable updates for pointer masking variables and thus enable pointer masking extension, Alexey Baturo, 2023/09/08
- [RFC v1 7/8] target/riscv: Update address modify functions to take into account pointer masking, Alexey Baturo, 2023/09/08