[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 7/9] target/riscv/tcg: add hash table insert helpers
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v4 7/9] target/riscv/tcg: add hash table insert helpers |
Date: |
Wed, 25 Oct 2023 10:49:59 -0300 |
Latest patches added several g_hash_table_insert() patterns. Add two
helpers, one for each user hash, to make the code cleaner.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++++------------
1 file changed, 16 insertions(+), 12 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 57026cfcca..cc7266b903 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -42,6 +42,18 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
GUINT_TO_POINTER(ext_offset));
}
+static void cpu_cfg_ext_add_user_opt(uint32_t ext_offset, bool value)
+{
+ g_hash_table_insert(multi_ext_user_opts, GUINT_TO_POINTER(ext_offset),
+ (gpointer)value);
+}
+
+static void cpu_misa_ext_add_user_opt(uint32_t bit, bool value)
+{
+ g_hash_table_insert(misa_ext_user_opts, GUINT_TO_POINTER(bit),
+ (gpointer)value);
+}
+
static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,
bool enabled)
{
@@ -696,9 +708,7 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v,
const char *name,
return;
}
- g_hash_table_insert(misa_ext_user_opts,
- GUINT_TO_POINTER(misa_bit),
- (gpointer)value);
+ cpu_misa_ext_add_user_opt(misa_bit, value);
prev_val = env->misa_ext & misa_bit;
@@ -811,18 +821,14 @@ static void cpu_set_profile(Object *obj, Visitor *v,
const char *name,
continue;
}
- g_hash_table_insert(misa_ext_user_opts,
- GUINT_TO_POINTER(bit),
- (gpointer)value);
+ cpu_misa_ext_add_user_opt(bit, profile->enabled);
riscv_cpu_write_misa_bit(cpu, bit, profile->enabled);
}
for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
ext_offset = profile->ext_offsets[i];
- g_hash_table_insert(multi_ext_user_opts,
- GUINT_TO_POINTER(ext_offset),
- (gpointer)profile->enabled);
+ cpu_cfg_ext_add_user_opt(ext_offset, profile->enabled);
isa_ext_update_enabled(cpu, ext_offset, profile->enabled);
}
}
@@ -885,9 +891,7 @@ static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v,
const char *name,
multi_ext_cfg->name, lower);
}
- g_hash_table_insert(multi_ext_user_opts,
- GUINT_TO_POINTER(multi_ext_cfg->offset),
- (gpointer)value);
+ cpu_cfg_ext_add_user_opt(multi_ext_cfg->offset, value);
prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset);
--
2.41.0
- [PATCH v4 2/9] target/riscv/kvm: add 'rva22u64' flag as unavailable, (continued)
- [PATCH v4 2/9] target/riscv/kvm: add 'rva22u64' flag as unavailable, Daniel Henrique Barboza, 2023/10/25
- [PATCH v4 4/9] target/riscv/tcg: add MISA user options hash, Daniel Henrique Barboza, 2023/10/25
- [PATCH v4 8/9] target/riscv/tcg: honor user choice for G MISA bits, Daniel Henrique Barboza, 2023/10/25
- [PATCH v4 9/9] target/riscv/tcg: warn if profile exts are disabled, Daniel Henrique Barboza, 2023/10/25
- [PATCH v4 5/9] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Daniel Henrique Barboza, 2023/10/25
- [PATCH v4 7/9] target/riscv/tcg: add hash table insert helpers,
Daniel Henrique Barboza <=
- [PATCH v4 6/9] target/riscv/tcg: handle profile MISA bits, Daniel Henrique Barboza, 2023/10/25