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[PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi
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From: |
Max Chou |
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Subject: |
[PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi |
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Date: |
Wed, 25 Oct 2023 23:13:36 +0800 |
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi.
The rotate amount of vror.vi is defined by combining seperated bits.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
disas/riscv.c | 11 +++++++++++
disas/riscv.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 8e89e1d1157..6d60033abab 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4011,6 +4011,12 @@ static uint32_t operand_vzimm10(rv_inst inst)
return (inst << 34) >> 54;
}
+static uint32_t operand_vzimm6(rv_inst inst)
+{
+ return ((inst << 37) >> 63) << 5 |
+ ((inst << 44) >> 59);
+}
+
static uint32_t operand_bs(rv_inst inst)
{
return (inst << 32) >> 62;
@@ -4393,6 +4399,11 @@ static void decode_inst_operands(rv_decode *dec, rv_isa
isa)
dec->imm = operand_vimm(inst);
dec->vm = operand_vm(inst);
break;
+ case rv_codec_vror_vi:
+ dec->rd = operand_rd(inst);
+ dec->rs2 = operand_rs2(inst);
+ dec->imm = operand_vzimm6(inst);
+ break;
case rv_codec_vsetvli:
dec->rd = operand_rd(inst);
dec->rs1 = operand_rs1(inst);
diff --git a/disas/riscv.h b/disas/riscv.h
index b242d73b25e..19e5ed2ce63 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -152,6 +152,7 @@ typedef enum {
rv_codec_v_i,
rv_codec_vsetvli,
rv_codec_vsetivli,
+ rv_codec_vror_vi,
rv_codec_zcb_ext,
rv_codec_zcb_mul,
rv_codec_zcb_lb,
--
2.34.1
- [PATCH 02/14] target/riscv: Expose Zvkt extension property, (continued)
- [PATCH 02/14] target/riscv: Expose Zvkt extension property, Max Chou, 2023/10/25
- [PATCH 03/14] target/riscv: Add cfg property for Zvkb extension, Max Chou, 2023/10/25
- [PATCH 04/14] target/riscv: Replace Zvbb checking by Zvkb, Max Chou, 2023/10/25
- [PATCH 05/14] target/riscv: Expose Zvkb extension property, Max Chou, 2023/10/25
- [PATCH 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions, Max Chou, 2023/10/25
- [PATCH 07/14] target/riscv: Expose Zvkn[c|g] extnesion properties, Max Chou, 2023/10/25
- [PATCH 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions, Max Chou, 2023/10/25
- [PATCH 09/14] target/riscv: Expose Zvks[c|g] extnesion properties, Max Chou, 2023/10/25
- [PATCH 10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions, Max Chou, 2023/10/25
- [PATCH 11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format, Max Chou, 2023/10/25
- [PATCH 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi,
Max Chou <=
- [PATCH 13/14] disas/riscv: Add support for vector crypto extensions, Max Chou, 2023/10/25
- [PATCH 14/14] disas/riscv: Replace TABs with space, Max Chou, 2023/10/25