[PATCH v5 00/10] RVA22U64 profile support

[Daniel Henrique Barboza]

Based-on: 20231023153927.435083-1-dbarboza@ventanamicro.com
("[PATCH v3 0/4] riscv: zicntr/zihpm flags and disable support")

Hi,

This patch contains a change proposed by Drew in v4: document in the
code, in the profile description, our reasoning behind assuming that
QEMU already support all cache related named features/synthetic
extensions.

It also contains a new patch (patch 1). This patch adds support for the
zic64b named feature, which is a fancy way the RVA22U64 spec found to
mandate 64 bytes cache blocks. QEMU already assumes a 64 byte default
value for them, but in v4 we weren't considering the use case where the
user enables the RVA22U64 profile and then happens to change the block
sizes, i.e. a profile violation.

We're implementing it by adding the flag and, if the flag is user (or
profile) set, and we're not using 64 bytes cache blocks (meaning the
user changed the block sizes in the command line), send an user warning
and disable the flag. zic64b is an 'almost extension' in a sense that
we're not adding it in the riscv,isa DT.

I am aware that the existence of these exotic "named features that
aren't real extensions" profile-only flags in QEMU will raise questions
(How will the kernel detect it if we're not writing the riscv,isa DT?
Will it imply that if all cache sizes are 64 then we have a zic64b
system?). We'll add zic64b and any other named feature in the riscv,isa
when/if it makes sense. For now we just want to get RVA22U64 out of the
door as feature-complete as possible.

No other changes made. Patches based on top of:

[PATCH v3 0/4] riscv: zicntr/zihpm flags and disable support

Patches missing acks: patch 1

Changes from v4:
- patch 1 (new):
  - add zic64b support
- patch 2 (former 1):
  - add a comment in the profile definition explaining that QEMU does not
    implement cache  and we consider all cache-related named features as
    always enabled
  - add zic64b in the profile definition
- v4 link: 
20231025135001.531224-1-dbarboza@ventanamicro.com/">https://lore.kernel.org/qemu-riscv/20231025135001.531224-1-dbarboza@ventanamicro.com/

Daniel Henrique Barboza (10):
  target/riscv/tcg: add 'zic64b' support
  target/riscv: add rva22u64 profile definition
  target/riscv/kvm: add 'rva22u64' flag as unavailable
  target/riscv/tcg: add user flag for profile support
  target/riscv/tcg: add MISA user options hash
  target/riscv/tcg: add riscv_cpu_write_misa_bit()
  target/riscv/tcg: handle profile MISA bits
  target/riscv/tcg: add hash table insert helpers
  target/riscv/tcg: honor user choice for G MISA bits
  target/riscv/tcg: warn if profile exts are disabled

 target/riscv/cpu.c         |  43 +++++-
 target/riscv/cpu.h         |  15 ++
 target/riscv/cpu_cfg.h     |   1 +
 target/riscv/kvm/kvm-cpu.c |   7 +-
 target/riscv/tcg/tcg-cpu.c | 275 +++++++++++++++++++++++++++++++------
 5 files changed, 296 insertions(+), 45 deletions(-)

-- 
2.41.0