[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v5 04/10] target/riscv/tcg: add user flag for profile support
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v5 04/10] target/riscv/tcg: add user flag for profile support |
Date: |
Wed, 25 Oct 2023 20:44:53 -0300 |
The TCG emulation implements all the extensions described in the
RVA22U64 profile, both mandatory and optional. The mandatory extensions
will be enabled via the profile flag. We'll leave the optional
extensions to be enabled by hand.
Given that this is the first profile we're implementing in TCG we'll
need some ground work first:
- all profiles declared in riscv_profiles[] will be exposed to users.
TCG is the main accelerator we're considering when adding profile
support in QEMU, so for now it's safe to assume that all profiles in
riscv_profiles[] will be relevant to TCG;
- we'll not support user profile settings for vendor CPUs. The flags
will still be exposed but users won't be able to change them. The idea
is that vendor CPUs in the future can enable profiles internally in
their cpu_init() functions, showing to the external world that the CPU
supports a certain profile. But users won't be able to enable/disable
it;
- Setting a profile to 'true' means 'enable all mandatory extensions of
this profile, setting it to 'false' means disabling all its mandatory
extensions. Regular left-to-right option order will determine the
resulting CPU configuration, i.e. the following QEMU command line:
-cpu rv64,zicbom=false,zifencei=false,rva22u64=true
Enables all rva22u64 mandatory extensions, including 'zicbom' and
'zifencei', while this other command line:
-cpu rv64,rva22u64=true,zicbom=false,zifencei=false
Enables all mandatory rva22u64 extensions, and then disable both zicbom
and zifencei.
For now we'll handle multi-letter extensions only. MISA extensions need
additional steps that we'll take care later.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/tcg/tcg-cpu.c | 53 ++++++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index ac5f65a757..c1eddf17fd 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -794,6 +794,57 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)
}
}
+static void cpu_set_profile(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ RISCVCPUProfile *profile = opaque;
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ bool value;
+ int i, ext_offset;
+
+ if (object_dynamic_cast(obj, TYPE_RISCV_DYNAMIC_CPU) == NULL) {
+ error_setg(errp, "Profile %s only available for generic CPUs",
+ profile->name);
+ return;
+ }
+
+ if (!visit_type_bool(v, name, &value, errp)) {
+ return;
+ }
+
+ profile->user_set = true;
+ profile->enabled = value;
+
+ for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
+ ext_offset = profile->ext_offsets[i];
+
+ g_hash_table_insert(multi_ext_user_opts,
+ GUINT_TO_POINTER(ext_offset),
+ (gpointer)profile->enabled);
+ isa_ext_update_enabled(cpu, ext_offset, profile->enabled);
+ }
+}
+
+static void cpu_get_profile(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ RISCVCPUProfile *profile = opaque;
+ bool value = profile->enabled;
+
+ visit_type_bool(v, name, &value, errp);
+}
+
+static void riscv_cpu_add_profiles(Object *cpu_obj)
+{
+ for (int i = 0; riscv_profiles[i] != NULL; i++) {
+ const RISCVCPUProfile *profile = riscv_profiles[i];
+
+ object_property_add(cpu_obj, profile->name, "bool",
+ cpu_get_profile, cpu_set_profile,
+ NULL, (void *)profile);
+ }
+}
+
static bool cpu_ext_is_deprecated(const char *ext_name)
{
return isupper(ext_name[0]);
@@ -918,6 +969,8 @@ static void riscv_cpu_add_user_properties(Object *obj)
riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts);
+ riscv_cpu_add_profiles(obj);
+
for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
qdev_property_add_static(DEVICE(obj), prop);
}
--
2.41.0
- [PATCH v5 00/10] RVA22U64 profile support, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 03/10] target/riscv/kvm: add 'rva22u64' flag as unavailable, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 02/10] target/riscv: add rva22u64 profile definition, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 04/10] target/riscv/tcg: add user flag for profile support,
Daniel Henrique Barboza <=
- [PATCH v5 06/10] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 05/10] target/riscv/tcg: add MISA user options hash, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 01/10] target/riscv/tcg: add 'zic64b' support, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 08/10] target/riscv/tcg: add hash table insert helpers, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 07/10] target/riscv/tcg: handle profile MISA bits, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 10/10] target/riscv/tcg: warn if profile exts are disabled, Daniel Henrique Barboza, 2023/10/25
- [PATCH v5 09/10] target/riscv/tcg: honor user choice for G MISA bits, Daniel Henrique Barboza, 2023/10/25