+ .name = "rva22u64",
+ .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC,
+ .ext_offsets = {
+ CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
+ CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
+ CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),
+ CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr),
+ CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom),
+ CPU_CFG_OFFSET(ext_zicboz),
+
+ RISCV_PROFILE_EXT_LIST_END
+ }
+};
+
+RISCVCPUProfile *riscv_profiles[] = {
+ &RVA22U64, NULL,
+};