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[PATCH v7 05/16] target/riscv/tcg: add 'zic64b' support
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v7 05/16] target/riscv/tcg: add 'zic64b' support |
Date: |
Tue, 31 Oct 2023 17:39:05 -0300 |
zic64b is defined in the RVA22U64 profile [1] as a named feature for
"Cache blocks must be 64 bytes in size, naturally aligned in the address
space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64
profile mandates this feature, meaning that applications using this
profile expects 64 bytes cache blocks.
To make the upcoming RVA22U64 implementation complete, we'll zic64b as
a 'named feature', not a regular extension. This means that:
- it won't be exposed to users;
- it won't be written in riscv,isa.
This will be extended to other named extensions in the future, so we're
creating some common boilerplate for them as well.
zic64b is default to 'true' since we're already using 64 bytes blocks.
If any cache block size (cbo{m,p,z}_blocksize) is changed to something
different than 64, zic64b is set to 'false'.
Our profile implementation will then be able to check the current state
of zic64b and take the appropriate action (e.g. throw a warning).
[1] https://github.com/riscv/riscv-profiles/releases/download/v1.0/profiles.pdf
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 6 ++++++
target/riscv/cpu.h | 1 +
target/riscv/cpu_cfg.h | 1 +
target/riscv/tcg/tcg-cpu.c | 14 ++++++++++++++
4 files changed, 22 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7e5ad76eff..f284604857 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1408,6 +1408,12 @@ const RISCVCPUMultiExtConfig
riscv_cpu_experimental_exts[] = {
DEFINE_PROP_END_OF_LIST(),
};
+const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
+ MULTI_EXT_CFG_BOOL("zic64b", zic64b, true),
+
+ DEFINE_PROP_END_OF_LIST(),
+};
+
/* Deprecated entries marked for future removal */
const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8efc4d83ec..bf12f34082 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -745,6 +745,7 @@ typedef struct RISCVCPUMultiExtConfig {
extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[];
extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[];
extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[];
+extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[];
extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[];
extern Property riscv_cpu_options[];
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index 2203b4c45b..f61a8434c4 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -108,6 +108,7 @@ struct RISCVCPUConfig {
bool ext_smepmp;
bool rvv_ta_all_1s;
bool rvv_ma_all_1s;
+ bool zic64b;
uint32_t mvendorid;
uint64_t marchid;
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index f54069d06f..8aa17ffaa2 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -264,6 +264,18 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU
*cpu)
}
}
+static void riscv_cpu_validate_zic64b(RISCVCPU *cpu)
+{
+ cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 &&
+ cpu->cfg.cbop_blocksize == 64 &&
+ cpu->cfg.cboz_blocksize == 64;
+}
+
+static void riscv_cpu_validate_named_features(RISCVCPU *cpu)
+{
+ riscv_cpu_validate_zic64b(cpu);
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
@@ -586,6 +598,8 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error
**errp)
return;
}
+ riscv_cpu_validate_named_features(cpu);
+
if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
--
2.41.0
- [PATCH v7 00/16] rv64i CPU, RVA22U64 profile support, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 01/16] target/riscv: create TYPE_RISCV_VENDOR_CPU, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 02/16] target/riscv/tcg: do not use "!generic" CPU checks, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 03/16] target/riscv: add rv64i CPU, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 04/16] target/riscv: add zicbop extension flag, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 05/16] target/riscv/tcg: add 'zic64b' support,
Daniel Henrique Barboza <=
- [PATCH v7 06/16] riscv-qmp-cmds.c: expose named features in cpu_model_expansion, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 07/16] target/riscv: add rva22u64 profile definition, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 08/16] target/riscv/kvm: add 'rva22u64' flag as unavailable, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 09/16] target/riscv/tcg: add user flag for profile support, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 10/16] target/riscv/tcg: add MISA user options hash, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 11/16] target/riscv/tcg: add riscv_cpu_write_misa_bit(), Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 12/16] target/riscv/tcg: handle profile MISA bits, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 13/16] target/riscv/tcg: add hash table insert helpers, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 14/16] target/riscv/tcg: honor user choice for G MISA bits, Daniel Henrique Barboza, 2023/10/31
- [PATCH v7 15/16] target/riscv/tcg: validate profiles during finalize, Daniel Henrique Barboza, 2023/10/31