Re: [PATCH v10 08/18] target/riscv: add rva22u64 profile definition

[Daniel Henrique Barboza]

On 11/21/23 05:13, Jerry Shih wrote:
> On Nov 3, 2023, at 21:46, Daniel Henrique Barboza <dbarboza@ventanamicro.com> 
> wrote:
> > +/*
> > + * RVA22U64 defines some 'named features' or 'synthetic extensions'
> > + * that are cache related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
> > + * and Zicclsm. We do not implement caching in QEMU so we'll consider
> > + * all these named features as always enabled.
> > + *
>
> Hi Daniel,
>
> If the cache related extensions are `ignored/assumed enabled`, why don't
> we export them in `riscv,isa`?

These aren't extensions, but 'named features'. They don't have a riscv,isa. 
There's
no DT bindings for them.

> If we try to check the RVA22 profile in linux kernel running with qemu, the
> isa string is not match RVA22 profile.

The kernel would check profile compatibility by matching the riscv,isa of the 
actual
extensions, as expected, but then it would need to check these 'named features'
in other fashion. For example, in patch 06, zic64b would be asserted by checking
if all block sizes are 64 bytes.

I agree that this is over-complicated and checking everything in riscv,isa 
would make
things easier. For now these named extensions don't have DT bindings, thus we 
can't
add them to the DT. The kernel doesn't seem to care about their existence in 
the DT
either.

TBH a better place for this discussion is the kernel mailing list. Thanks,



Daniel



> Thanks,
> Jerry