qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

About RISCV’s Performance Counters and QEMU


From: ELIO VINCIGUERRA
Subject: About RISCV’s Performance Counters and QEMU
Date: Fri, 1 Dec 2023 14:27:37 +0000

Hi everybody, I recently started using RISCV architectures, I would need a way to access “hpmcounter[3-31]” registers using QEMU emulator.

The kernel used for simulations is a C program, not a heavy operating system, which is why I would need to access the registers mentioned before via assembly.

Trivially accessing any of those registers always returns zero.

The question is:
Are these registers enabled in QEMU? If not, is it possible to enable them or are they hardwired to zero? How?

Trying to access the registers “cycle”, “instret” and “time” the values come out to be non-zero, which is why I think it is also possible to enable “hpmcounter[3-31]”, but the mode of operation is unknown to me, can anyone help me?

Regards,
Elio

reply via email to

[Prev in Thread] Current Thread [Next in Thread]