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Re: [PATCH 2/3] target/riscv: Add step to validate 'B' extension
From: |
Andrew Jones |
Subject: |
Re: [PATCH 2/3] target/riscv: Add step to validate 'B' extension |
Date: |
Thu, 11 Jan 2024 14:09:31 +0100 |
On Tue, Jan 09, 2024 at 05:07:36PM +0000, Rob Bradford wrote:
> If the B extension is enabled warn if the user has disabled any of the
> required extensions that are part of the 'B' extension. Conversely
> enable the extensions that make up the 'B' extension if it is enabled.
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> ---
> target/riscv/tcg/tcg-cpu.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index fda54671d5..f10871d352 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -273,6 +273,35 @@ static void
> riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
> }
> }
>
> +static void riscv_cpu_validate_b(RISCVCPU *cpu)
> +{
> + const char *warn_msg = "RVB mandates disabled extension %s";
> +
> + if (!cpu->cfg.ext_zba) {
> + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) {
> + cpu->cfg.ext_zba = true;
> + } else {
> + warn_report(warn_msg, "zba");
> + }
> + }
> +
> + if (!cpu->cfg.ext_zbb) {
> + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) {
> + cpu->cfg.ext_zbb = true;
> + } else {
> + warn_report(warn_msg, "zbb");
> + }
> + }
> +
> + if (!cpu->cfg.ext_zbs) {
> + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) {
> + cpu->cfg.ext_zbs = true;
> + } else {
> + warn_report(warn_msg, "zbs");
> + }
> + }
> +}
> +
> /*
> * Check consistency between chosen extensions while setting
> * cpu->cfg accordingly.
> @@ -309,6 +338,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
> env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
> }
>
> + if (riscv_has_ext(env, RVB)) {
> + riscv_cpu_validate_b(cpu);
> + }
> +
> if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
> error_setg(errp,
> "I and E extensions are incompatible");
> --
> 2.43.0
>
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
- Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, (continued)
- Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Daniel Henrique Barboza, 2024/01/10
- Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Andrew Jones, 2024/01/11
- Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Andrew Jones, 2024/01/11
- Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Rob Bradford, 2024/01/11
- Re: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Andrew Jones, 2024/01/12
- Re: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Rob Bradford, 2024/01/12
- Re: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Ved Shanbhogue, 2024/01/12
Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Andrew Jones, 2024/01/11
[PATCH 2/3] target/riscv: Add step to validate 'B' extension, Rob Bradford, 2024/01/09
[PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type, Rob Bradford, 2024/01/09