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[PATCH v4 09/13] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v4 09/13] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ() |
Date: |
Mon, 22 Jan 2024 13:11:03 -0300 |
Calculate the maximum vector size possible, 'max_sz', which is the size
in bytes 'vlenb' multiplied by the max value of LMUL (LMUL = 8, when
s->lmul = 3).
'max_sz' is then shifted right by 'scale', expressed as '3 - s->lmul',
which is clearer than doing 'scale = lmul - 3' and then using '-scale'
in the shift right.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index d743675262..b4663b6e1f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1160,12 +1160,12 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
/*
* MAXSZ returns the maximum vector size can be operated in bytes,
* which is used in GVEC IR when vl_eq_vlmax flag is set to true
- * to accerlate vector operation.
+ * to accelerate vector operation.
*/
static inline uint32_t MAXSZ(DisasContext *s)
{
- int scale = s->lmul - 3;
- return s->cfg_ptr->vlen >> -scale;
+ int max_sz = s->cfg_ptr->vlenb * 8;
+ return max_sz >> (3 - s->lmul);
}
static bool opivv_check(DisasContext *s, arg_rmrr *a)
--
2.43.0
- [PATCH v4 00/13] target/riscv: add 'cpu->cfg.vlenb', remove, Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 01/13] target/riscv: add 'vlenb' field in cpu->cfg, Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 02/13] target/riscv/csr.c: use 'vlenb' instead of 'vlen', Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 03/13] target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen', Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 04/13] target/riscv/insn_trans/trans_rvbf16.c.inc: use cpu->cfg.vlenb, Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 05/13] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb', Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 06/13] target/riscv/insn_trans/trans_rvvk.c.inc: use 'vlenb', Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 07/13] target/riscv/vector_helper.c: use 'vlenb', Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 08/13] target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl), Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 09/13] target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ(),
Daniel Henrique Barboza <=
- [PATCH v4 10/13] target/riscv/cpu.h: use 'vlenb' in vext_get_vlmax(), Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 11/13] target/riscv: change vext_get_vlmax() arguments, Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 12/13] trans_rvv.c.inc: use vext_get_vlmax() in trans_vrgather_v*(), Daniel Henrique Barboza, 2024/01/22
- [PATCH v4 13/13] target/riscv/cpu.c: remove cpu->cfg.vlen, Daniel Henrique Barboza, 2024/01/22
- Re: [PATCH v4 00/13] target/riscv: add 'cpu->cfg.vlenb', remove, Alistair Francis, 2024/01/23