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[PATCH v4 6/6] target/riscv: Promote svade to a normal extension
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v4 6/6] target/riscv: Promote svade to a normal extension |
Date: |
Thu, 15 Feb 2024 19:39:55 -0300 |
From: Andrew Jones <ajones@ventanamicro.com>
Named features are extensions which don't make sense for users to
control and are therefore not exposed on the command line. However,
svade is an extension which makes sense for users to control, so treat
it like a "normal" extension. The default is false, even for the max
cpu type, since QEMU has always implemented hardware A/D PTE bit
updating, so users must opt into svade (or get it from a CPU type
which enables it by default).
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 9 ++-------
target/riscv/tcg/tcg-cpu.c | 6 ++++++
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 7598daa162..fd0c7efdda 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1474,6 +1474,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
+ MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
@@ -1589,7 +1590,6 @@ const RISCVCPUMultiExtConfig
riscv_cpu_experimental_exts[] = {
* and priv_ver like regular extensions.
*/
const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
- MULTI_EXT_CFG_BOOL("svade", ext_svade, true),
MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
/*
@@ -2237,8 +2237,6 @@ static RISCVCPUProfile RVA22U64 = {
* Other named features that we already implement: Sstvecd, Sstvala,
* Sscounterenw
*
- * Named features that we need to enable: svade
- *
* The remaining features/extensions comes from RVA22U64.
*/
static RISCVCPUProfile RVA22S64 = {
@@ -2250,10 +2248,7 @@ static RISCVCPUProfile RVA22S64 = {
.ext_offsets = {
/* rva22s64 exts */
CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
- CPU_CFG_OFFSET(ext_svinval),
-
- /* rva22s64 named features */
- CPU_CFG_OFFSET(ext_svade),
+ CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade),
RISCV_PROFILE_EXT_LIST_END
}
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index ccfb7b2dd3..ab6db817db 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -1282,6 +1282,12 @@ static void riscv_init_max_cpu_extensions(Object *obj)
isa_ext_update_enabled(cpu, prop->offset, true);
}
+ /*
+ * Some extensions can't be added without backward compatibilty concerns.
+ * Disable those, the user can still opt in to them on the command line.
+ */
+ cpu->cfg.ext_svade = false;
+
/* set vector version */
env->vext_ver = VEXT_VERSION_1_00_0;
--
2.43.0
- [PATCH v4 0/6] riscv: named features riscv,isa, 'svade' rework, Daniel Henrique Barboza, 2024/02/15
- [PATCH v4 1/6] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile(), Daniel Henrique Barboza, 2024/02/15
- [PATCH v4 2/6] target/riscv: add riscv,isa to named features, Daniel Henrique Barboza, 2024/02/15
- [PATCH v4 3/6] target/riscv: add remaining named features, Daniel Henrique Barboza, 2024/02/15
- [PATCH v4 4/6] target/riscv: Reset henvcfg to zero, Daniel Henrique Barboza, 2024/02/15
- [PATCH v4 5/6] target/riscv: Gate hardware A/D PTE bit updating, Daniel Henrique Barboza, 2024/02/15
- [PATCH v4 6/6] target/riscv: Promote svade to a normal extension,
Daniel Henrique Barboza <=
- Re: [PATCH v4 0/6] riscv: named features riscv,isa, 'svade' rework, Alistair Francis, 2024/02/15