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[PATCH RFC 1/8] target/riscv: Add properties for Indirect CSR Access ext
From: |
Atish Patra |
Subject: |
[PATCH RFC 1/8] target/riscv: Add properties for Indirect CSR Access extension |
Date: |
Fri, 16 Feb 2024 16:01:27 -0800 |
From: Kaiwen Xue <kaiwenx@rivosinc.com>
This adds the properties for sxcsrind. Definitions of new registers and
implementations will come with future patches.
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
---
target/riscv/cpu.c | 4 ++++
target/riscv/cpu_cfg.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8af99ed2f6de..ff7c6c7c380e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -152,10 +152,12 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
+ ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
+ ISA_EXT_DATA_ENTRY(sscsrind, PRIV_VERSION_1_12_0, ext_sscsrind),
ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
@@ -1348,6 +1350,8 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
/* Defaults for standard extensions */
MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false),
+ MULTI_EXT_CFG_BOOL("smcsrind", ext_smcsrind, false),
+ MULTI_EXT_CFG_BOOL("sscsrind", ext_sscsrind, false),
MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
index eabbecb8f962..b9086464752e 100644
--- a/target/riscv/cpu_cfg.h
+++ b/target/riscv/cpu_cfg.h
@@ -74,6 +74,8 @@ struct RISCVCPUConfig {
bool ext_smstateen;
bool ext_sstc;
bool ext_smcntrpmf;
+ bool ext_smcsrind;
+ bool ext_sscsrind;
bool ext_svadu;
bool ext_svinval;
bool ext_svnapot;
--
2.34.1
- [PATCH RFC 0/8] Add Counter delegation ISA extension support, Atish Patra, 2024/02/16
- [PATCH RFC 1/8] target/riscv: Add properties for Indirect CSR Access extension,
Atish Patra <=
- [PATCH RFC 2/8] target/riscv: Decouple AIA processing from xiselect and xireg, Atish Patra, 2024/02/16
- [PATCH RFC 3/8] target/riscv: Enable S*stateen bits for AIA, Atish Patra, 2024/02/16
- [PATCH RFC 5/8] target/riscv: Add smcdeleg/ssccfg properties, Atish Patra, 2024/02/16
- [PATCH RFC 6/8] target/riscv: Add counter delegation definitions, Atish Patra, 2024/02/16
- [PATCH RFC 7/8] target/riscv: Add select value range check for counter delegation, Atish Patra, 2024/02/16
- [PATCH RFC 4/8] target/riscv: Support generic CSR indirect access, Atish Patra, 2024/02/16
- [PATCH RFC 8/8] target/riscv: Add counter delegation/configuration support, Atish Patra, 2024/02/16
- Re: [PATCH RFC 0/8] Add Counter delegation ISA extension support, Daniel Henrique Barboza, 2024/02/21