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[PATCH 11/65] target/riscv: Add unit-stride store instructions for XThea
From: |
Huang Tao |
Subject: |
[PATCH 11/65] target/riscv: Add unit-stride store instructions for XTheadVector |
Date: |
Fri, 12 Apr 2024 15:36:41 +0800 |
XTheadVector unit-stride store instructions diff from RVV1.0 in the following
points:
1. Different mask reg layout.
2. Different vector reg element width.
3. Different tail/masked elements process policy.
4. Different check policy.
The detials of the difference are the same as strided store instruction, as
unit-stride is the special case of strided operations.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 26 ++++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 59 +++++++++++++++++--
target/riscv/xtheadvector_helper.c | 31 ++++++++++
3 files changed, 112 insertions(+), 4 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index f2fa8425b3..eb31784e18 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1361,3 +1361,29 @@ DEF_HELPER_5(th_vlwu_v_w, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(th_vlwu_v_w_mask, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(th_vlwu_v_d, void, ptr, ptr, tl, env, i32)
DEF_HELPER_5(th_vlwu_v_d_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsb_v_b, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsb_v_b_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsb_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsb_v_h_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsb_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsb_v_w_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsb_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsb_v_d_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsh_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsh_v_h_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsh_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsh_v_w_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsh_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsh_v_d_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsw_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsw_v_w_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsw_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vsw_v_d_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vse_v_b, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vse_v_b_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vse_v_h, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vse_v_h_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vse_v_w, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vse_v_w_mask, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vse_v_d, void, ptr, ptr, tl, env, i32)
+DEF_HELPER_5(th_vse_v_d_mask, void, ptr, ptr, tl, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index eb910acf40..9b88ea2fa4 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -398,6 +398,61 @@ GEN_TH_TRANS(th_vlbu_v, 4, r2nfvm, ld_us_op_th,
ld_us_check_th)
GEN_TH_TRANS(th_vlhu_v, 5, r2nfvm, ld_us_op_th, ld_us_check_th)
GEN_TH_TRANS(th_vlwu_v, 6, r2nfvm, ld_us_op_th, ld_us_check_th)
+/*
+ * This function is almost the copy of st_us_op, except:
+ * 1) different data encoding.
+ * 2) XTheadVector has more situations, depending on SEW.
+ */
+static bool st_us_op_th(DisasContext *s, arg_r2nfvm *a, uint8_t seq)
+{
+ uint32_t data = 0;
+ gen_helper_ldst_us_th *fn;
+ static gen_helper_ldst_us_th * const fns[2][4][4] = {
+ /* masked unit stride load and store */
+ { { gen_helper_th_vsb_v_b_mask, gen_helper_th_vsb_v_h_mask,
+ gen_helper_th_vsb_v_w_mask, gen_helper_th_vsb_v_d_mask },
+ { NULL, gen_helper_th_vsh_v_h_mask,
+ gen_helper_th_vsh_v_w_mask, gen_helper_th_vsh_v_d_mask },
+ { NULL, NULL,
+ gen_helper_th_vsw_v_w_mask, gen_helper_th_vsw_v_d_mask },
+ { gen_helper_th_vse_v_b_mask, gen_helper_th_vse_v_h_mask,
+ gen_helper_th_vse_v_w_mask, gen_helper_th_vse_v_d_mask } },
+ /* unmasked unit stride store */
+ { { gen_helper_th_vsb_v_b, gen_helper_th_vsb_v_h,
+ gen_helper_th_vsb_v_w, gen_helper_th_vsb_v_d },
+ { NULL, gen_helper_th_vsh_v_h,
+ gen_helper_th_vsh_v_w, gen_helper_th_vsh_v_d },
+ { NULL, NULL,
+ gen_helper_th_vsw_v_w, gen_helper_th_vsw_v_d },
+ { gen_helper_th_vse_v_b, gen_helper_th_vse_v_h,
+ gen_helper_th_vse_v_w, gen_helper_th_vse_v_d } }
+ };
+
+ fn = fns[a->vm][seq][s->sew];
+ if (fn == NULL) {
+ return false;
+ }
+
+ data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA_TH, VM, a->vm);
+ data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul);
+ data = FIELD_DP32(data, VDATA_TH, NF, a->nf);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
+}
+
+static bool st_us_check_th(DisasContext *s, arg_r2nfvm* a)
+{
+ return (require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ th_check_reg(s, a->rd, false) &&
+ th_check_nf(s, a->rd, a->nf));
+}
+
+GEN_TH_TRANS(th_vsb_v, 0, r2nfvm, st_us_op_th, st_us_check_th)
+GEN_TH_TRANS(th_vsh_v, 1, r2nfvm, st_us_op_th, st_us_check_th)
+GEN_TH_TRANS(th_vsw_v, 2, r2nfvm, st_us_op_th, st_us_check_th)
+GEN_TH_TRANS(th_vse_v, 3, r2nfvm, st_us_op_th, st_us_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
@@ -411,10 +466,6 @@ TH_TRANS_STUB(th_vleff_v)
TH_TRANS_STUB(th_vlbuff_v)
TH_TRANS_STUB(th_vlhuff_v)
TH_TRANS_STUB(th_vlwuff_v)
-TH_TRANS_STUB(th_vsb_v)
-TH_TRANS_STUB(th_vsh_v)
-TH_TRANS_STUB(th_vsw_v)
-TH_TRANS_STUB(th_vse_v)
TH_TRANS_STUB(th_vlxb_v)
TH_TRANS_STUB(th_vlxh_v)
TH_TRANS_STUB(th_vlxw_v)
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index 7566ab8e31..5c05cd5aa6 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -405,3 +405,34 @@ GEN_TH_LD_US(th_vlhu_v_w, uint16_t, uint32_t, ldhu_w,
clearl_th)
GEN_TH_LD_US(th_vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq_th)
GEN_TH_LD_US(th_vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl_th)
GEN_TH_LD_US(th_vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq_th)
+
+/* similar to GEN_GEN_VEXT_ST_US, change the function */
+#define GEN_TH_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \
+void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t stride = th_nf(desc) * sizeof(MTYPE); \
+ th_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \
+ NULL, sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
+} \
+ \
+void HELPER(NAME)(void *vd, void *v0, target_ulong base, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ th_ldst_us(vd, base, env, desc, STORE_FN, NULL, \
+ sizeof(ETYPE), sizeof(MTYPE), GETPC()); \
+}
+
+GEN_TH_ST_US(th_vsb_v_b, int8_t, int8_t , stb_b)
+GEN_TH_ST_US(th_vsb_v_h, int8_t, int16_t, stb_h)
+GEN_TH_ST_US(th_vsb_v_w, int8_t, int32_t, stb_w)
+GEN_TH_ST_US(th_vsb_v_d, int8_t, int64_t, stb_d)
+GEN_TH_ST_US(th_vsh_v_h, int16_t, int16_t, sth_h)
+GEN_TH_ST_US(th_vsh_v_w, int16_t, int32_t, sth_w)
+GEN_TH_ST_US(th_vsh_v_d, int16_t, int64_t, sth_d)
+GEN_TH_ST_US(th_vsw_v_w, int32_t, int32_t, stw_w)
+GEN_TH_ST_US(th_vsw_v_d, int32_t, int64_t, stw_d)
+GEN_TH_ST_US(th_vse_v_b, int8_t, int8_t , ste_b)
+GEN_TH_ST_US(th_vse_v_h, int16_t, int16_t, ste_h)
+GEN_TH_ST_US(th_vse_v_w, int32_t, int32_t, ste_w)
+GEN_TH_ST_US(th_vse_v_d, int64_t, int64_t, ste_d)
--
2.44.0
- [PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation, (continued)
- [PATCH 01/65] riscv: thead: Add th.sxstatus CSR emulation, Huang Tao, 2024/04/12
- [PATCH 02/65] target/riscv: Reuse th_csr.c to add user-mode csrs, Huang Tao, 2024/04/12
- [PATCH 03/65] target/riscv: Add properties for XTheadVector extension, Huang Tao, 2024/04/12
- [PATCH 04/65] target/riscv: Override some csr ops for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 05/65] target/riscv: Add mlen in DisasContext, Huang Tao, 2024/04/12
- [PATCH 06/65] target/riscv: Implement insns decode rules for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 07/65] target/riscv: implement th.vsetvl{i} for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 08/65] target/riscv: Add strided load instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 09/65] target/riscv: Add strided store instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 10/65] target/riscv: Add unit-stride load instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 11/65] target/riscv: Add unit-stride store instructions for XTheadVector,
Huang Tao <=
- [PATCH 12/65] target/riscv: Add indexed load instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 13/65] target/riscv: Add indexed store instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 14/65] target/riscv: Add unit-stride fault-only-first instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 15/65] target/riscv: Add vector amo operations for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 16/65] target/riscv: Add single-width integer add and subtract instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 17/65] target/riscv: Add widening integer add/subtract instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 18/65] target/riscv: Add integer add-with-carry/sub-with-borrow instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 19/65] target/riscv: Add bitwise logical instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 20/65] target/riscv: Add single-width bit shift instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 21/65] target/riscv: Add narrowing integer right shift instructions for XTheadVector, Huang Tao, 2024/04/12