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[PATCH 31/65] target/riscv: Add single-width average add and sub instruc
From: |
Huang Tao |
Subject: |
[PATCH 31/65] target/riscv: Add single-width average add and sub instructions for XTheadVector |
Date: |
Fri, 12 Apr 2024 15:37:01 +0800 |
The instructions have the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 17 +++++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 12 ++++---
target/riscv/vector_helper.c | 8 ++---
target/riscv/vector_internals.h | 5 +++
target/riscv/xtheadvector_helper.c | 36 +++++++++++++++++++
5 files changed, 69 insertions(+), 9 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c5156d9939..aab2979328 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1918,3 +1918,20 @@ DEF_HELPER_6(th_vssub_vx_b, void, ptr, ptr, tl, ptr,
env, i32)
DEF_HELPER_6(th_vssub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vssub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(th_vssub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(th_vaadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vaadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vaadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vaadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vasub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vasub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vasub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vasub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(th_vaadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vaadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vaadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vaadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vasub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vasub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vasub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(th_vasub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index e60da5b237..59da1e4b3f 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -1710,17 +1710,19 @@ GEN_OPIVX_TRANS_TH(th_vssub_vx, opivx_check_th)
GEN_OPIVI_TRANS_TH(th_vsaddu_vi, IMM_ZX, th_vsaddu_vx, opivx_check_th)
GEN_OPIVI_TRANS_TH(th_vsadd_vi, IMM_SX, th_vsadd_vx, opivx_check_th)
+/* Vector Single-Width Averaging Add and Subtract */
+GEN_OPIVV_TRANS_TH(th_vaadd_vv, opivv_check_th)
+GEN_OPIVV_TRANS_TH(th_vasub_vv, opivv_check_th)
+GEN_OPIVX_TRANS_TH(th_vaadd_vx, opivx_check_th)
+GEN_OPIVX_TRANS_TH(th_vasub_vx, opivx_check_th)
+GEN_OPIVI_TRANS_TH(th_vaadd_vi, IMM_SX, th_vaadd_vx, opivx_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vaadd_vv)
-TH_TRANS_STUB(th_vaadd_vx)
-TH_TRANS_STUB(th_vaadd_vi)
-TH_TRANS_STUB(th_vasub_vv)
-TH_TRANS_STUB(th_vasub_vx)
TH_TRANS_STUB(th_vsmul_vv)
TH_TRANS_STUB(th_vsmul_vx)
TH_TRANS_STUB(th_vwsmaccu_vv)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 8664a3d4ef..ea1e449174 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -2323,7 +2323,7 @@ static inline uint8_t get_round(int vxrm, uint64_t v,
uint8_t shift)
return 0; /* round-down (truncate) */
}
-static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a,
+int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a,
int32_t b)
{
int64_t res = (int64_t)a + b;
@@ -2332,7 +2332,7 @@ static inline int32_t aadd32(CPURISCVState *env, int
vxrm, int32_t a,
return (res >> 1) + round;
}
-static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a,
+int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a,
int64_t b)
{
int64_t res = a + b;
@@ -2398,7 +2398,7 @@ GEN_VEXT_VX_RM(vaaddu_vx_h, 2)
GEN_VEXT_VX_RM(vaaddu_vx_w, 4)
GEN_VEXT_VX_RM(vaaddu_vx_d, 8)
-static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a,
+int32_t asub32(CPURISCVState *env, int vxrm, int32_t a,
int32_t b)
{
int64_t res = (int64_t)a - b;
@@ -2407,7 +2407,7 @@ static inline int32_t asub32(CPURISCVState *env, int
vxrm, int32_t a,
return (res >> 1) + round;
}
-static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a,
+int64_t asub64(CPURISCVState *env, int vxrm, int64_t a,
int64_t b)
{
int64_t res = (int64_t)a - b;
diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h
index a70ebdabe4..19f174f4c8 100644
--- a/target/riscv/vector_internals.h
+++ b/target/riscv/vector_internals.h
@@ -303,4 +303,9 @@ uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a,
uint8_t b);
uint16_t ssubu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b);
uint32_t ssubu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b);
uint64_t ssubu64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b);
+
+int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b);
+int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b);
+int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b);
+int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b);
#endif /* TARGET_RISCV_VECTOR_INTERNALS_H */
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index 5e21ab2e07..06ac5940b7 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -2258,3 +2258,39 @@ GEN_TH_VX_RM(th_vssub_vx_b, 1, 1, clearb_th)
GEN_TH_VX_RM(th_vssub_vx_h, 2, 2, clearh_th)
GEN_TH_VX_RM(th_vssub_vx_w, 4, 4, clearl_th)
GEN_TH_VX_RM(th_vssub_vx_d, 8, 8, clearq_th)
+
+THCALL(TH_OPIVV2_RM, th_vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32)
+THCALL(TH_OPIVV2_RM, th_vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32)
+THCALL(TH_OPIVV2_RM, th_vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32)
+THCALL(TH_OPIVV2_RM, th_vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64)
+GEN_TH_VV_RM(th_vaadd_vv_b, 1, 1, clearb_th)
+GEN_TH_VV_RM(th_vaadd_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_RM(th_vaadd_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_RM(th_vaadd_vv_d, 8, 8, clearq_th)
+
+THCALL(TH_OPIVX2_RM, th_vaadd_vx_b, OP_SSS_B, H1, H1, aadd32)
+THCALL(TH_OPIVX2_RM, th_vaadd_vx_h, OP_SSS_H, H2, H2, aadd32)
+THCALL(TH_OPIVX2_RM, th_vaadd_vx_w, OP_SSS_W, H4, H4, aadd32)
+THCALL(TH_OPIVX2_RM, th_vaadd_vx_d, OP_SSS_D, H8, H8, aadd64)
+GEN_TH_VX_RM(th_vaadd_vx_b, 1, 1, clearb_th)
+GEN_TH_VX_RM(th_vaadd_vx_h, 2, 2, clearh_th)
+GEN_TH_VX_RM(th_vaadd_vx_w, 4, 4, clearl_th)
+GEN_TH_VX_RM(th_vaadd_vx_d, 8, 8, clearq_th)
+
+THCALL(TH_OPIVV2_RM, th_vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32)
+THCALL(TH_OPIVV2_RM, th_vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32)
+THCALL(TH_OPIVV2_RM, th_vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32)
+THCALL(TH_OPIVV2_RM, th_vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64)
+GEN_TH_VV_RM(th_vasub_vv_b, 1, 1, clearb_th)
+GEN_TH_VV_RM(th_vasub_vv_h, 2, 2, clearh_th)
+GEN_TH_VV_RM(th_vasub_vv_w, 4, 4, clearl_th)
+GEN_TH_VV_RM(th_vasub_vv_d, 8, 8, clearq_th)
+
+THCALL(TH_OPIVX2_RM, th_vasub_vx_b, OP_SSS_B, H1, H1, asub32)
+THCALL(TH_OPIVX2_RM, th_vasub_vx_h, OP_SSS_H, H2, H2, asub32)
+THCALL(TH_OPIVX2_RM, th_vasub_vx_w, OP_SSS_W, H4, H4, asub32)
+THCALL(TH_OPIVX2_RM, th_vasub_vx_d, OP_SSS_D, H8, H8, asub64)
+GEN_TH_VX_RM(th_vasub_vx_b, 1, 1, clearb_th)
+GEN_TH_VX_RM(th_vasub_vx_h, 2, 2, clearh_th)
+GEN_TH_VX_RM(th_vasub_vx_w, 4, 4, clearl_th)
+GEN_TH_VX_RM(th_vasub_vx_d, 8, 8, clearq_th)
--
2.44.0
- [PATCH 21/65] target/riscv: Add narrowing integer right shift instructions for XTheadVector, (continued)
- [PATCH 21/65] target/riscv: Add narrowing integer right shift instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 22/65] target/riscv: Add integer compare instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 23/65] target/riscv: Add integer min/max instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 24/65] target/riscv: Add single-width integer multiply instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 25/65] target/riscv: Add integer divide instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 26/65] target/riscv: Add widening integer multiply instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 27/65] target/riscv: Add single-width integer multiply-add instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 28/65] target/riscv: Add widening integer multiply-add instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 29/65] target/riscv: Add integer merge and move instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 30/65] target/riscv: Add single-width saturating add and sub instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 31/65] target/riscv: Add single-width average add and sub instructions for XTheadVector,
Huang Tao <=
- [PATCH 32/65] target/riscv: Add single-width fractional mul with rounding and saturation for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 33/65] target/riscv: Add widening saturating scaled multiply-add instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 34/65] target/riscv: Add single-width scaling shift instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 35/65] target/riscv: Add narrowing fixed-point clip instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 36/65] target/riscv: Add single-width floating-point add/sub instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 37/65] target/riscv: Add widening floating-point add/sub instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 38/65] target/riscv: Add single-width floating-point multiply/divide instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 39/65] target/riscv: Add widening floating-point multiply instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 40/65] target/riscv: Add single-width floating-point fused multiply-add instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 41/65] target/riscv: Add widening floating-point fused mul-add instructions for XTheadVector, Huang Tao, 2024/04/12