Hello,
I'm currently trying to run a RISC-V bare-metal kernel on QEMU that uses the
floating point extension F.
It seems like this extension, besides D, is enabled automatically in QEMU.
In fact, the floating point registers can be examined successfully using
GDB.
However, when the first floating point instruction is reached in the program
execution (in this case flw), an illegal instruction trap is raised. The
kernel itself is compiled using these flags: -march=rv32imaf -mabi=ilp32f
Is there something I am missing? Perhaps, the FPU needs to be enabled in
some way?