[avr-gcc-list] ATmega16 ADC at High Clock Rates

[User Tomdean]

The ATmega16 datasheet states, in part,

  By default, the successive approximation circuitry requires an input
  clock frequency between 50 kHz and 200 kHz to get maximum
  resoultion.  If a lower resolution than 10 bits is needed, the input
  clock frequency to the ADC can be higher than 200 kHz to get a
  higher sample rate.

The datasheet does not specify the reduction in resolution due to a
higher clock rate.

Before I measure, does anyone know the reduction in resoultion, say,
at 1 mHz?  2 mHz?

tomdean