[Commit-gnuradio] r5189 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations

[thottelt]

Author: thottelt
Date: 2007-04-28 19:26:12 -0600 (Sat, 28 Apr 2007)
New Revision: 5189

Modified:
   
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
   gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
still broken2

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
===================================================================
--- 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
        2007-04-28 21:53:47 UTC (rev 5188)
+++ 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
        2007-04-29 01:26:12 UTC (rev 5189)
@@ -26,9 +26,9 @@
     
     /* Local wires for FIFO connections */
     wire                      [2**LOG2_N-1:0]     fifo_resets ;
-    wire                      [2**LOG2_N-1:0]     fifo_we ;
+    reg                       [2**LOG2_N-1:0]     fifo_we ;
     wire                      [2**LOG2_N-1:0]     fifo_re ;
-    wire                      [FIFO_WIDTH-1:0]    fifo_wdata[2**LOG2_N-1:0] ;
+    reg                       [FIFO_WIDTH-1:0]    fifo_wdata[2**LOG2_N-1:0] ;
     wire                      [FIFO_WIDTH-1:0]    fifo_rdata[2**LOG2_N-1:0] ;
     wire                      [2**LOG2_N-1:0]     fifo_rempty ;
     wire                      [2**LOG2_N-1:0]     fifo_rfull ;
@@ -40,8 +40,8 @@
     reg     [LOG2_N-1:0]            fifo_wselect ;
     
     /* Used to convert 16 bits usbdata to the 32 bits wide fifo */
-    reg                             second_half ;
-    reg     [BUS_WIDTH-1:0]         msb_usbdata ;
+    reg                             word_complete ;
+    reg     [BUS_WIDTH-1:0]         write_data_delayed ;
     
     /* Assign have_space to empty flag of currently selected write FIFO */
     assign have_space = fifo_wempty[fifo_wselect] ;
@@ -74,7 +74,7 @@
         if (reset)
           begin
             fifo_wselect <= {2**LOG2_N{1'b0}} ;
-            second_half <= 0;
+            word_complete <= 0;
           end
             
         if (fifo_wfull[fifo_wselect])
@@ -82,9 +82,18 @@
             
         if (write_enable)
           begin
-            second_half = ~second_half ;
-            if (!second_half)
-                msb_usbdata <= write_data ;
+            word_complete <= ~word_complete ;
+            
+            if (word_complete)
+                fifo_wdata[fifo_wselect] <= {write_data_delayed, write_data} ;
+            else
+                write_data_delayed <= write_data ;
+              
+            /* Avoid to continue to write in the previous fifo when we have 
+               just swichted to the next one */ 
+            fifo_we[fifo_wselect-1] <= 0 ;
+            
+            fifo_we[fifo_wselect] <= write_enable & word_complete ;
           end
     end
     
@@ -94,8 +103,6 @@
         begin : generate_single_packet_fifos
             assign fifo_re[i] = (fifo_rselect == i) ? read_enable : 1'b0 ;
             assign fifo_resets[i] = (fifo_rselect == i) ? skip_packet : 1'b0 ;
-            assign fifo_we[i] = (fifo_wselect == i) ? write_enable & 
~second_half : 1'b0 ;
-            assign fifo_wdata[i] = {msb_usbdata, write_data} ;
             fifo_512 single_packet_fifo(.wrclk  ( usb_clock      ),
                                         .rdclk  ( fpga_clock     ),
                                         .aclr   ( fifo_resets[i] ), 

Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf    2007-04-28 
21:53:47 UTC (rev 5188)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf    2007-04-29 
01:26:12 UTC (rev 5189)
@@ -253,7 +253,7 @@
 Project_File_3 = ./fake_fx2.v
 Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177707503 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 
cover_expr 0 dont_compile 0 cover_stmt 0
 Project_File_4 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177721745 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
14 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177809758 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
14 dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
 Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1177718984 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8 
dont_compile 0 cover_expr 0 cover_stmt 0
 Project_File_6 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v